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Low Power Design Methods:Design Flows and KitsShushanik Karapetyan1st year PhD StudentSynopsys Armenia Educational Department,State Engineering University of ArmeniaMoscowMarch 23, 2011Copyright 2011 Synopsys, Inc.
Outline Low Power Design Flows Library requirements for Low Power Design Example of 90nm EDKCopyright 2011 Synopsys, Inc.
Conventional Design FlowSystem and Software ArchitecturePower Management should betaken into account at the earliestdesign stagesRTL ImplementationLogic simulationLogic SynthesisAlmost every step of design flowneed to be modified for LPDTiming AnalysisFormal VerificationPhysical SynthesisSignoffCopyright 2011 Synopsys, Inc.
Power-Aware Design FlowSystem and Software ArchitectureRTL ImplementationLogic simulationChoose appropriatepower intent, design styles etc.Implement power intentin appropriate formatPower aware simulationand analysisLogic SynthesisTiming AnalysisFormal VerificationAutomate synthesisof LPD techniquesPower-aware verificationneeded to reveal powerRelated bugsPhysical SynthesisSignoffSignoff tools must be voltageaware for silicon successCopyright 2011 Synopsys, Inc.
LPD Techniques Automation LevelsClock GatingENCGLeakageQDFFMulti-thresholdDelayLow-Vth Std-Vth High-VthClkClock GateAutomaticallyNo special treatment neededOFFPower gating0.9V0.9VAutomatically0.9VMulti Voltage0.9V0.7V0.9VSpecification of power intent (UPF)Copyright 2011 Synopsys, Inc.
Unified Power Format (UPF): NecessityLanguageSpecification ofpower intentInteroperableCan be freely usedamong EDA tools(open standard)HardwareDescriptionLanguages(Verilog, VHDL, etc.)- Vendor –SpecificFormats --UPF Copyright 2011 Synopsys, Inc.
Specifying Power IntentA0.9VPeripheryPower Domain0.9/OFF isoLSLSOFFBLS0.7V/1.2VC0.9VLSOperation Scenario(OFF, 0.9V, 0.7V)(0.9V, 0.9V, 1.2V)MV with power gatingCopyright 2011 Synopsys, Inc.Supply Network
MV with Power Gating ExampleVDDAA0.9VVDDBVDD0.9/OFFRRVDDControlVDDVOFF opyright 2011 Synopsys, Inc.
UPF: Power 0.7V/1.2VLSVSSC0.9V VDDLSVDDB isoLSLSVSSVSSVSSCopyright 2011 Synopsys, Inc.
UPF: Supply tageLevel (V)PowerDomainVDD0.9CVDDA0.7BVDDB1.2BVDDVVirtual 0.9AVSSCommonGroundA/B/CVDDVOFFLS isoLSLSVSSControlBVDDA0.7V/1.2VLS0.9V VDDLSVDDBVSSCVSSVSSCopyright 2011 Synopsys, Inc.
UPF: PeripheryVDDAUPFA0.9VVDDBVDDVDDLevel Shifters between A and B0.9/OFFRRRequired PeripheryVDDVLevel Shifters between B and COFFIsolation between C and ALSRetention Cell inside A isoLSLSVSSControlBVDDA0.7V/1.2VLSVSSC0.9V VDDLSVDDBControl Block inside AVSSVSSCopyright 2011 Synopsys, Inc.
UPF: State edOFF1.20.9Not AllowedOFFLS isoLSLSVSSControlBVDDA0.7V/1.2VLSVDDBLSVSSC0.9V VDDVSSVSSCopyright 2011 Synopsys, Inc.
Design Flow Modification with UPFDesign SpecificationRTLEx. SynopsysDesign CompilerInitial UPFInitial Power Intent LPD Technique strategy Implementation detailsLogic SynthesisGate LevelEx. SynopsysIC Compiler Initial UPF description ismodified during design Gate LevelUPF Supply net connections Special cellsPhysical SynthesisGate LevelPG Gate Level PhysicalUPFCopyright 2011 Synopsys, Inc. Modifications to low-powercircuit structures
Design Compiler Visual UPFStrategies VisualizationSupply portPD boundaryBlock PD primarypower netPower SwitchISO locationparentwithbackup powerdefinedRetention registerLS strategydefined inUPFTop PD primaryground netCopyright 2011 Synopsys, Inc.
IC Compiler UPF Placement Placement respectsvoltage areaboundary Special Level Shifterand Isolation Cellsplacement Special cellsplaced closer toVA boundaryLS cellsISO cellsCopyright 2011 Synopsys, Inc.
Library Requirements for LPD Special cellsSpecial versions of libraryCharacterization in additional cornersAdditional views/files/attributesCopyright 2011 Synopsys, Inc.
90nm EDK: Digital Standard Cell LibraryDigital Standard Cell Library (DSCL)Aimed at optimizing the main characteristics of designed IcsContains 340 cells, cell list compiled based on the requirements for educationaldesignsTypical combinational and sequential logic cells for different drive strengthsTypical combinational and sequentialSpecial cells for different styles LPDInverters/BuffersLogic GatesFlip-Flops(regular scan)Isolation CellsLevel ShiftersRetentionFlip-FlopsLatchesDelay LinesPhysical(Antenna diode)Clock gatingAlways-onBuffersPower GatingProvides the support of IC design with different core voltages to minimizedynamic and leakage power.Copyright 2011 Synopsys, Inc.
Special Cells for LPD: Level Shifter1.2LSLSLSLSLS0.90.7LSLevel ShiftersCopyright 2011 Synopsys, Inc.
Level ShifterVDDLDVDDLVDDHVDDHDQQVSSVSSLogic Symbol of Low to High Level ShifterLogic Symbol of High to Low Level ShifterLow to High Level Shifter Truth TableHigh to Low Level Shifter Truth TableD (0.8V)Q (1.2V)D (1.2V)Q (0.8V)00001111Copyright 2011 Synopsys, Inc.
Level Shifter Physical owLow-to-HighCopyright 2011 Synopsys, Inc.
Level Shifter (High to Low) PhysicalDesignVDDLHighvoltageareasVDDHLow voltageareaVDDLCopyright 2011 Synopsys, Inc.
Level Shifter (Low to High) PhysicalDesignVDDHLow voltageareaVDDLHHighvoltageareasHVDDHCopyright 2011 Synopsys, Inc.
Special Cells for LPD: Isolation CellsPower Gating0.90.9OFF/0.7Isolation CellsCopyright 2011 Synopsys, Inc.
Isolation CellsDDQQISOISOLogic Symbol of Clamp 0Isolation Cell (Logic AND)Logic Symbol of Clamp 1Isolation Cell (Logic OR)Hold 0 Isolation Cell (Logic AND) Truth TableDISOQ010111X00Hold 1 Isolation Cell (Logic OR) Truth TableBypassmodeOutput clampedCopyright 2011 Synopsys, Inc.DISOQ000101X11Bypassmode
Isolation Cells: Physical DesignCopyright 2011 Synopsys, Inc.
Special Cells for LPD: Always-on BuffersPower Gating0.7 – 1.080.9OFF/0.7Always on cellsCopyright 2011 Synopsys, Inc.
Always-on BufferVDDGINPZVDD local(on/off)VSSLogic Symbol of Alwayson Non-Inverting BufferAlways onareaVDD global(always-on)Always on Non-InvertingBuffer Truth TableINVDDGVSSQ01001101VSS local(on/off)Copyright 2011 Synopsys, Inc.
Special Cells for LPD: Always-on Isolation cellsAlways-onIsolation Cells0.70.9Copyright 2011 Synopsys, Inc.OFF/0.7
Always on Isolation CellsVDDVDDGVDD VDDGDDQQISOISOVSSVSSLogic Symbol of Clamp 0 Isolation Cell(Logic AND),Always OnLogic Symbol of Clamp 1 Isolation Cell(Logic OR), Always OnHold 0 Isolation Cell (Logic AND) Truth TableDISOQ010111X00Hold 1 Isolation Cell (Logic OR) Truth TableBypassmodeOutput clampedCopyright 2011 Synopsys, Inc.DISOQ000101X11Bypassmode
Isolation Cell (always-on) Physical DesignAlways on supplyAlways on areaCopyright 2011 Synopsys, Inc.
Special Cells for LPD: Enable levelshifters Combination of LevelShifter and ISO cellEnable levelshifters1.080.9Copyright 2011 Synopsys, Inc.OFF/0.7
Level Shifters With Active Low EnableVDDLVDDHVDDHENBVDDLENBLSUPENDQQDVSSVSSSymbol of High to Low Level ShifterActive Low Enable, Clamp 1Symbol of Low to High Level ShifterActive Low Enable, Clamp X11BypassmodeOutput clampedCopyright 2011 Synopsys, Inc.Bypassmode
Enable Level Shifter (low-to-high)Physical designLow voltageareaVDDHVDDLHighvoltageareasVDDHCopyright 2011 Synopsys, Inc.
State Retention RegistersState Retention RegistersRRRRRRCTR1.08V/OFF1.08V/OFF0.7Vsleep0.9V Retention Register - preservestatus while the logic is turned offCopyright 2011 Synopsys, Inc.
Retention Register Physical designAlways-on Power pinAlways on area, with highVthCopyright 2011 Synopsys, Inc.
Power GatesRRRRRRCTR1.08V/OFF1.08V/OFF0.7Vsleep0.9VPower Gates Retention Register - preservestatus while the logic is turned offCoarse Grain - Power Gates(switch cells)Copyright 2011 Synopsys, Inc.
Header CellsVDDGVDDGVDDVDDSLEEPSLEEPSLEEPOUTLogic Symbol of Header CellLogic Symbol of Header Cell(with SLEEPOUT output )Header Cell Truth TableHeader Cell (with SLEEPOUT output) Truth 11hi-z1Copyright 2011 Synopsys, Inc.
Header Cells Physical Designa. Header Cellb. Header Cell (with SLEEPOUT output)Copyright 2011 Synopsys, Inc.
Multi-Threshold ow-VthStd-VthLeakageMulti-Vth librariesALBLCLLow VthASBSCSStd VthAHBHCHHigh VthCopyright 2011 Synopsys, Inc.High-VthDelay
DSCL: Multi Threshold Versions of Cells For implementation of Multi-Vth technique thewhole DSCL is available in 3 versions (1020cells) All cells with Low– threshold voltage All cells with Standard – threshold voltage All cells with High– threshold voltageCopyright 2011 Synopsys, Inc.
Characterization Characterization computes cell parameter (e.g. delay, outputcurrent) depending on input variables: output load, input slew, etc. Characterization is preformed for various combinations of operatingconditions: process, voltage, temperature (also called PVT corners).slewInput SlewslewslewIoutCchar0.70.7 0.50.7 0.50.20.5 0.20.10.2 0.10.1Process: FastTemp:125oVoltage: 1.32vProcess: SlowTemp:-40o.023 .047 .065 .078 .091 Voltage: 1.08voutput cap.023 .047 .065 .078 .091 Process: TypicalTemp:25ooutput cap.023 .047 .065 .078 .091Voltage: 1.2voutput capCopyright 2011 Synopsys, Inc.
DSCL: Characterization CornersTTNT1p20vSSHT1p08vFFLT1p32vProcess(NMOS proc. –PMOS proc.)Typical - TypicalSlow - SlowFast - FastFFHT1p32vFast - FFLT0p90vTemperature (T)Power Supply (V)Notes25125-401.21.081.321251.32Typical cornerSlow cornerFast cornerHigh leakagecornerLow temperaturecorners-40Slow - Slow1.32-40Slow - Slow1.08Low Voltage Operating Conditions25Typical - Typical0.80125Slow - Slow0.70-40Fast - Fast0.90FFHT0p90vFast - Fast1250.90SSLT0p90vSSLT0p70vSlow - SlowSlow - Slow-40-400.900.70Copyright 2011 Synopsys, Inc.Typical cornerSlow cornerFast cornerHigh leakagecornerLow temperaturecorners
DSCL: Additional Data Power / ground (PG) pindefinitions are required forall cells in a library Defined as attributes in .lib Allows accurate definition ofmultiple power / ground pininformation Benefits Power domain drivensynthesis Automatic power netconnections PST-based optimization Verification of PG netlist vs.power domains Power switch verificationpg pin(VDD) {std cell main rail : true ;voltage name : VDD;pg type: primary power;}pg pin(VSS) {voltage name : VSS;pg type: primary ground;}Copyright 2011 Synopsys, Inc.
DSCL: Power Verilog Models Power Verilog models Separate verilog models withpower modelingmodule AND2X1(IN1,IN2,Q);output Q;input IN1,IN2;and (Q,IN2,IN1);endmodulemodule AND2X1 (IN1,IN2,Q,VDD,VSS);output Q;Modeling outputinput IN1,IN2;state dependenceinout VDD;inout VSS;on powerpower down iQ (Q, Qint, VDD, VSS);and (Qint,IN1,IN2);endmoduleprimitive power down (Q, Qint, vdd, vss);output Q;input Qint, vdd, vss;table0 1 0 : 0 ;1 1 0 : 1 ;? 0 0 : x ;? 0 1 : x ;? 1 1 : x ;? x ? : x ;? ? x : x ;endtableendprimitiveCopyright 2011 Synopsys, Inc.
DSCL: Special Cells for Low PowerTechniques (1) Power GatingsVDDG 5 cells with different loads Always onVDDGVDDINQAOnSLEEP 10 cells: 3 inverters, 3 buffers and4 DFFsVSS Retention cellsVDD 44 cells negedge/posedge, scanRETNVDDGQISOD Isolation cellsDISOCLKQN 8 cells with different logic, loadVSSCopyright 2011 Synopsys, Inc.Q
DSCL: Special Cells for Low PowerTechniques (2) Level shiftersVDDL 16 cells Low/High, High/Low, withor without enable, with differentloadsVDDHLSUPDQ Clock gatings: 11 cells with different loads, edges,and control (post/pre)VSSSEENL HVT CellsEN All logical cells are designed usingHVT, LVTCopyright 2011 Synopsys, Inc.CLKLATCHOBSGCLK
DSCL: Special Cells for Low PowerTechniques (3)Power Gates(MTCMOS)0.9V0.9V 0.9V0.9V0.7V 0.9VOFF0.9V0.9V 0.9VOFF0.9V0.7V 0.9VOFFS 0.9VR0.7V 0.9VIsolationCellsLevel ShiftersRetentionRegistersAlways OnLogicMultiple PowerDomainsSingle VoltageMultiple Voltage(MV)Domains Power Gating(shut down)Single VoltageNo StateRetention MV DomainsPower GatingNo StateRetention MV DomainsPower GatingState Retention Copyright 2011 Synopsys, Inc.
Low Power Design of ChipTop Developedwith DSCL: DC viewCopyright 2011 Synopsys, Inc.
Low Power Design of ChipTop Developedwith DSCL: ICC ViewCopyright 2011 Synopsys, Inc.
Conclusion Low Power Design requires significant design flow modifications UPF enables LPD flow automation Low Power design techniques have their huge impact on libraries SAED 90nm EDK DSCL includes all special cells needed for lowpower design techniques This 90nm EDK is currently in use in 235 universities of 37 countries This 90nm EDK is used inside Synopsys for education of customers Currently similar EDK is being developed for 32/28nm technology,initial release is planned in June 2011Copyright 2011 Synopsys, Inc.
Title: IC Design Introduction
