Memory TestinghFlasMemory Testing IntroductionhFlasPage1

Memory Testing Memory Devices Introduction Memory Testing Methodology Memory ATE & Integration Memory Testing Challenges Q&AContentsPage2

EPROMSRAMMemory TestingROMDRAMFLASHEEPROMNonvolatileVolatileMemory Non-Volatile - It doesn’t lose data after power is turned off- ROM,EPROM,EEPROM,Flash Volatile- the memory array loses its contents when power isremoved - SRAM,DRAMMemory device typePage3

Burstxxx psAccess ModeAccess TimeDH, IDMS,H,M,Q,EPCMajor VendorsMain ,T,IM,RyesBlock, Page,ColumnSect, Row,Col,(Partition)yesxx usAsR,W,ECEn,WEn,REn,CLE,ALEx8,x16IOx busFloating Gate2-8GNANDxx nsAs, BurstR,W,ECEn,WEn,OEnx16Logic Addr, A/D MultiplexFloating GateMemory TestingnoRow, Colxx nsAs, k,Row,ColR,WOperationPartitionCSn, RASn,CASn, WEnx8, x16Logic Addr4-6TT CRow, Column32-64M(p)SRAM512M-1GControl BitsIO BitsAddr InterfaceCellMainstreamDensityDRAMVolatileMemory Summary

Source : IntelSRAMDRAMFLASHROMEEPROMEPROMHigh DensityNonvolatileMemory TestingHigh SpeedUpdateableMemory FeaturesPage5

Memory TestingMemory Testing MethodologyPage6

Memory TestingPage7 Characterization Test– To identify the design and process window.– To finalized the datasheet specification.– Failure analysis and process debugging– Use many tool to get device characterization data, suchas bitmap, shmoo, Specs search, thermal stress.– Test time is not a issue Production Test– Acceptance test or go/ no-go test– Wafer sort, final test, burn in test, speed test, reliabilitytest.– Test time Cost .Characterization vs. Production Test

Input leakage testOutput leakage testOutput voltage testOutput short circuit testStatic/Dynamic Idd testODT(DDRII)Memory Testing Redundancy & Repair test (optional)Page8– Memory pattern test ( March, Diagonal, Checkerboard, Galloping )– Special test mode( stress, Vth, Icell, marginal test, data retention.)– Timing test ( Taa, Toe, Tce, Trc, etc) AC Functional test–––––– Continuity test – open/short DC parameter testBasic Memory Test Items

CP 3Laser RepairCP 2Bake 24 hrsat 250cDRAM OnlyDataRetentionCP 1Mark & PackQC / 70cFT 2/ 85 CMemory TestingAssemblyBurn InFT 1/ 25 CMemory Backend FlowPage9

Failurerate#of P/E cycle timeNormal life failure rateMemory TestingScreen failuresduring productionInfantMortalityWear outFailuresHigh voltage, High temperature(125 )– to screen out infant mortalitiesPurpose of Burn-InPage10

Memory TestingMemory Simplified Block DiagramPage11

X XmaxX 1X 011111 11 11 11 11111Y 0 Y 1Memory Testing .1/21 11 11 11 11 1Y Ymax1 11 11 1Access (R/W) Memory corePage12

X XmaxX 1X 00 11 0101 01 000 1011Y 0 Y 1Memory Testing .0 11 0101 00 11 0Y Ymax012/201Access (R/W) Memory corePage13

2x1 22x2 42x3 62x4 82x5 102x6 122x7 142x8 162x9 181x1 11x2 21x3 31x4 41x5 51x6 61x7 71x8 81x9 94x2 84x3 124x4 164x5 204x6 244x7 284x8 324x9 363x2 23x3 33x4 123x5 153x6 183x7 213x8 243x9 27 8x9 728x8 648x7 568x6 488x5 408x4 328x3 248x2 168x1 8Table 1/2Memory Testing4x1 4v.s. Multiple3x1 1Memory corePage149x9 819x8 729x7 639x6 549x5 459x4 369x3 279x2 189x1 9

v.s. MultipleTable 2/2Conditional Jumpfor loopMemory TestingMemory ATEY registerjC languageX registeriWe can use for loop and different variables andset boundary condition in C language, but how toimplement similar function in memory testerpattern?printf(“%d x %d %d\n”, i, j, ixj);for(j 1; j 10; j )for (i 1 ; i 10; i )Memory corePage15

v.s. LogicATE1/2Memory TestingLess than 10 Vectors lengthcycle6, Data nc;cycle5, y ,x (ymax), Address nr, Data cn, jump( ! loop, c--;loop:cycle4, d expect data, Data nc;cycle3, c (ymax 1)*(xmax 1)-1cycle2, ymax 0x3ff; xmax 0xffff;cycle1, y 0; x 0;Memory ATEPage16

Memory Testing64M Vectors lengthcycle0x4000000, x;addressv.s. Logiccycle1,Memory ATEPage17

Memory TestingMemory ATE & IntegrationPage18

Memory Testing High speed( 2G bps) EPA 100 ps Small jitter, Wide data EyeHigh Speed Tester : XDR, GDDR, DDRIIIpattern generator capability : APG, BM, ECR,.data width:32/64 or more,interleave,burst,refresh function,.high speedpowerful redundancy analysis repair NVM Tester : Flash, Mask ROM, EEPROM,. pattern generator capability : APG, BM, ECR. high voltage – Vcc, Vpp high density buffer memory for mask ROM powerful redundancy analysis repair Tester-Per-Site RAM Tester : DRAM,SRAMRequirement for memory ATEPage19


Idle Addr 1Idle Addr 2IdleIdle Addr 1Idle Addr 2Addr 1Idle Addr 2IdleIdle Addr 1Idle Addr 2IdleAddr 1Idle Addr 2IdleIdle Addr 1Idle Addr 2IdleIdle Addr 1Idle Addr 2IdleIdle Addr 1Addr 2IdleTest Time, Shared-Resource ArchitectureMemory TestingTest Time, Tester-Per-Site ArchitectureAddr 0Addr 1Addr 2Addr 3Addr 0Addr 1Addr 2Addr 3Addr 0Addr 1Addr 2 Addr 3Addr 0 Addr 1Addr 2Addr 3Addr 0Addr 1 Addr 2Addr 3Addr 0Addr 1 Addr 2Addr 3Addr 0 Addr 1Addr 2Addr 3Addr 0Addr 1Addr 2Addr 3Addr 0Addr 0Addr 0Addr 0Addr 0Addr 0Addr 0Addr 0Addr 3Addr 3Addr 3Addr 3Addr 3Addr 3Addr 3Addr 3Throughput ComparisonPage21IdleIdleIdleIdleIdleIdleIdle

APGMemory TestingATE Main Frame Block DiagramPage22

Memory TestingPage23Tester-Per-Site Parallel Test Architecture

ECR1X/Y/Z RegisterBMD RegisterECR2dl(0) - dl(15)ACAMMemory TestingECR0 - ECR15a(0) - a(31)ECR3ScrambleBM(0) - BM(15)dl(0) - dl(15)DUTPE0 - PE31Memory ATE(APG Resource)Page24

Page25High-volume manufacturing tester- Higher through-put- Lower cost-of-test- Easy maintainMemory TestingEngineering tester- Powerful / Flexible- Good debugging tools- Convenient- Easy migrating to productionEngineering to High-Volume Manufacturing

DSIMatrix – 24,576 pins128 sites – 4096 pinsPage26384 MCP, 384 NOR, 512 NANDFinal Test128 NOR, 320 NANDMemory TestingWafer Sort144 sites – 4608 pins4 sites – 128 pins2 TD skip row, 1 TD full wafer300mm Wafer ProbingEngineeringMCP, NOR, NAND developmentEng. Matrix – 768 pinsInterface/Interconnect technology

TesterHandler(FT)Page27Load BoardEngineer/OperatorTest result(Wafer Map)Server/NetworkMemory TestingProber(CP)Probe Card Tester Test head Prober(CP) / Handler(FT) Load board Probe card Test program Server/CIM systemTest Cell Environment

Final TestConfigurationMemory TestingWafer SortConfigurationPage28Economical Test Solution for Memory

Page29WS 300mm probecard1 Touchdown @ 100% efficiencyMemory Testing144 Test Sites ensure the fastest test [email protected] up to 288 devices in parallelWS interface for full300mm probingWS 1TD Probe Card solution

2304 I/O ChannelsVacuum Compression(Pogos)Memory Testing4608 I/O ChannelsMechanical Compression(XZIF)WS InterfacePage30

Memory TestingV5400 keep out area is 10” or 250mmV5400 vs. V4400V4400 pad density is 70mmV5400 pad density is 40mmPage3124% more probe card areaDouble the I/O density75% more keep out areaV5400 vs. V4400V4400 probe card is 355mmV5400 probe card is 440mmWS Interface – Probe Card

Memory TestingFT Interface: HiFixPage32

Cable assemblies(signal and DPS lines)Up to 16 HSM sitesPage33Trigger and reference connectorsfor calibration robotMemory TestingDPS wiring board for 8 DPS channels8 boards in totalHiFix Components

Debug toolsMemory Testing Mix of parts is increasing- Flash, DRAM, SRAM Increase Parallelism High SpeedPage34 High throughput Flexible configuration Reduced system costMemory Test Challenges

2 3 GbpsGDDR4 6.4 8GbpsXDR2XDR3Memory TestingPage35 DDR I/O speed islimited by “Physics” Expect New MemoryTechnology?GbpsDDR4?8 12Gbps nm Process technology is used to address speed & density (cost) Bandwidth demand drive speed of High-Speed DRAMsSource: SEC, Japan Rambus Symposium,June 04, Timing shows QS / MPVerigy’s ExtrapolationHigh-Speed Memory Device Roadmap

Memory TestingDDRIII MemoryPage36

MemoryManagementTIADelay Linesand FormattersWaveformMemoryHSM3600 Sub-Module(4 Channels)Memory ATE on a Single Chip(Test-Processor Per-Pin)Cage 6Cage 2HSM3600 Card(32 Channels)Water CooledCage 5Memory TestingCage 3Cage 7Page37 TRUE “Memory ATE Per-Pin” enabled by the Test-Processor TechnologyDACsARMcoreResultAPG per-pin ProcessingError CaptureMemoryIO &BroadcastCage 1RAMBUS CellCage 4High Speed Solution: Per-Pin ProcessorVectorCopy / Edit Functions SequencerBackFrontCage 8

Test ProcessorTest ProcessorDUAL UAL LEVELCOMPARATORVOLVcomVILIOHVIHDRIVER50 ΩTo HPPMU1 per cagePPMUP/FValue MeasurementTo HPPMU1 per cagePPMUP/FMemory Testing1 per 16 ch Board(2 on 1 board) ADCFront-end (Pin Electronics)CLAMPVCLVCHThird Level50 ΩACTIVELOAD -CLAMPVCL50 ΩDIFFERENTIALRECEIVERACTIVELOADVCHThird Level50 ΩPin 3Pin 1DUTPage38High Speed Solution: HW Free APG16chMUX

Memory TestingRepeating Patterns on a PinPage39High Speed Solution: Per-Pin Complier

Debug toolsMemory Testing Mix of parts is increasing- Flash, DRAM, SRAM Increase Parallelism High SpeedPage40 High throughput Flexible configuration Reduced system costMemory Test Challenges

Memory TestingMulti Chip Package (MCP )Page41

Intel256Mb StrataFlashSamsungSemiconductor256Mb NAND Flash,128Mb Mobile DRAMSpansion128Mb NOR,32Mb pSRAMMemory TestingA streaming video phone with 0.3MP Camera100% of modern cell phonesuse MCPsPage42Source: iSuppli Corp.

2) Dynamic APG minimizestest time and allows forconcurrent testing1) Dynamic Interface designto access different MemorypartsMemory TestingDynamic Interface: MatrixPage43

Debug toolsMemory Testing Mix of parts is increasing- Flash, DRAM, SRAM Increase Parallelism High SpeedPage44 High throughput Flexible configuration Reduced system costMemory Test Challenges

Dual LevelComparatorsActive Fan-out ChannelWire-OR ChannelTransmission LineStandard Pin ChannelDUTDUTDUTDUTDUTDUTDUTMemory TestingActive Fan-out with Compare ChannelDriverPage45Page 45 Better Signal Quality (Yield) High Parallelism (Throughput) Better Cost Parallel Reads (Throughput) Better Signal Quality (Yield) High Parallelism (Throughput) Better Cost Serial Reads (Throughput) High Parallelism (Throughput) Lowest Cost Degraded Signal Quality (Yield) Device Interaction (Yield) Serial Reads (Throughput) Good Signal Quality (Yield) Low Parallelism (Throughput) High CostIncrease Parallelism: PE Share

Memory Testing-2BABAVSS-ilimitSide effect at PE Share1/2Page46Page 46

Site1t1 0matchedlength 110ps t1-2matchedlength 90ps t2-3- Clock- DQ/DQSmatchedlength 120pstalign /- 320psSiteN t(N-1)-N tN 320talign /- 200psSiteN-1tN-1 200NON-SHAREDtalign /- 110psSite2t2 1102/2Memory TestingPage47– for the shared pins the fixture delay values compensate the delay to site 1 only for site 1 there is no change compared to a non-shared application For a driver sharing application (by-N sharing) the timing reference isthe socket of site 1- Address- CommandSHAREDSHARED PINSTiming ReferenceSide effect at PE Share

Debug toolsMemory Testing Mix of parts is increasing- Flash, DRAM, SRAM Increase Parallelism High SpeedPage48 High throughput Flexible configuration Reduced system costMemory Test Challenges

READWRITEMemory TestingIO turn-around time(here: 12ns @ 1Gbps data rate)READWRITETiming DiagramREADPage49WRITE

Memory Testing‘Oscilloscope’ integrated into test systemScope viewPage50

Memory Testing State-of-the-art andeasy to use!Zoom-InZoom-InPage51 Overlay – Different layers represented by colors Zoom IN/OUT Detail View with Logical / Topological / Physical Adr True Topological ViewBitMap Viewer

PATTERN ToolMemory TestingPage52

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Memory Testing Page8 Basic Memory Test Items Continuity test –open/short DC parameter test – Input leakage test – Output leakage test – Output voltage test – Output short circuit test – Static/Dynamic Iddtest – ODT(DDRII) AC Functional test – Timing test ( Taa, Toe, Tce, Trc, etc) – Memory pat