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Application ReportSNOA405A – May 2004 – Revised May 2004AN-1205 Electrical Performance of PackagesABSTRACTThis note is a snapshot of electrical performance of National's IC packages. It is provided to helpdesigners get an idea about electrical parasitics associated with the package, and help them compare theelectrical performance of different packages. The electrical performance of a package is usually expressedin terms of resistance (R), inductance (L), and capacitance (C). Example R-L-C data is provided forNational's package types.1234ContentsIntroduction .1.1RESISTANCE .1.2INDUCTANCE .1.3CAPACITANCE .1.4FREQUENCY LIMITATIONS OF R-L-C PARAMETERS .Circuit Model of a Package Lead .Example R-L-C Values for Packages .3.1LAMINATE BASED CSP (CHIP-SCALE PACKAGE) .3.2BGA PACKAGES .Wirebonds .2222333457List of Figures1Inductance of a Signal Loop . 22Equivalent of three package leads. 33Laminate CSP packages (not to scale) . 54Ball Grid Array packages1Frequency limitations of RLC parameters . 32Example RLC values for lead-frame based packages and micro SMD3Example RLC data for CSP packages . 54Example RLC Characteristics of BGAs (without planes) . 65AC Inductance - EBGA packages6Resistance and Capacitance - EBGA packages . 77Wirebond inductance . 7.6List of Tables.46All trademarks are the property of their respective owners.SNOA405A – May 2004 – Revised May 2004Submit Documentation FeedbackAN-1205 Electrical Performance of PackagesCopyright 2004, Texas Instruments Incorporated1

Introduction1www.ti.comIntroductionThis note is a snapshot of electrical performance of National's IC packages. It is provided to helpdesigners get an idea about electrical parasitics associated with the package, and help them compare theelectrical performance of different packages. The electrical performance of a package is usually expressedin terms of resistance (R), inductance (L), and capacitance (C). Example R-L-C data is provided forNational's package types.1.1RESISTANCEResistance is the cause of IR drops in the package. DC resistance is the resistance of a conductor whenthe entire cross section of the conductor is carrying current. At higher frequencies, the current isconcentrated along the surface of the conductor, due to skin effect. AC resistance increases withfrequency, because as the frequency increases, skin depth decreases, and the available cross section forthe current flow decreases. AC resistance varies linearly with length of the conductor, but not with respectto cross sectional area.1.2INDUCTANCEInductance (L) is defined as the relationship between the following for a closed current path: flux linkage (λ) and current flow (i): λ L i or time varying voltage (v) and current (i): v L di /dtOn an IC package, signals propagate in and out through the signal leads and return through the powerleads. The closed current path (or loop) is thus formed by signal leads together with power or groundleads. It is also possible to calculate inductance for an open circuit path, or a section of a closed loop(e.g., just a single lead). This is called partial inductance. Using this concept, the inductancecontributions of different elements in the loop (and their interactions) can be separated into differentinductance elements. This allows the designer to determine return paths and noise by simulation. It ispossible to determine the total loop inductance of an IO signal (returning through the power lead) or adifferential pair using partial self and mutual inductance. (See Figure 1).DC and AC Inductance: DC Inductance is calculated assuming that the current flows through the entirecross section of the conductor. AC inductance is calculated assuming that the skin depth is smallcompared to the cross section of the conductor, and current flows only on the surface of the conductors.Both DC and AC Inductance can be provided for packages. To determine which inductance is appropriatefor your application, please see the section "Frequency limitations of R-L-C parameters".Figure 1. Inductance of a Signal Loop1.3CAPACITANCESelf capacitance is the capacitance of any element to "ground". In package electrical models, the plane onthe PC board is assumed to be an ideal ground. Thus, self capacitance of any package element is thecapacitance of that element to the board plane. Mutual capacitance is the capacitance between any twoelements. For example, in a lumped model of ball grid array package, capacitance from a package traceto the package VSS plane is mutual capacitance.2AN-1205 Electrical Performance of PackagesCopyright 2004, Texas Instruments IncorporatedSNOA405A – May 2004 – Revised May 2004Submit Documentation Feedback

Circuit Model of a Package Leadwww.ti.com1.4FREQUENCY LIMITATIONS OF R-L-C PARAMETERSAs long as the conductor lengths are small compared to the maximum sinusoidal frequency of the signal,the lumped R-L-C approximation of the element is appropriate. For digital ICs, a lumped model isappropriate for a maximum lead length of 60 tr (tr is rise time in nanoseconds and length is inmillimeters). When using lumped elements, it is important to know which parameters (DC or AC) shouldbe used. Table 1 gives this information.Transmission line models or distributed models should be used for high frequencies. To determine if yourproduct requires this analysis, contact your local National Semiconductor technical representative.Table 1. Frequency limitations of RLC parametersParameterValid Frequency RangeDC ResistanceLeadframe packages: DC to 500 kHzSubstrate packages: DC to 5 MHzAC ResistanceLeadframe packages: 500 kHz to any freq.Substrate packages: 5 MHz to any freq.DC InductanceLeadframe packages: DC to 10 MHzSubstrate packages: DC to 100 MHzAC InductanceCapacitance2Leadframe packages: 10 MHz to any frequency provided lumped model is adequate.Substrate packages: 10 MHz to any frequency provided lumped model is adequate.From DC to any frequency, as long as dielectric loss can be neglected.Circuit Model of a Package LeadNational Semiconductor defines package models in terms of their T-equivalent circuits. Each lead has twoterminals - a "source" and a "sink" - representing its two ends. In a T-equivalent circuit, the leadinductance and resistance are divided in two parts, and placed on either sides of the lead capacitance.Figure 2 shows a T-equivalent model of three leads. The leads are labeled "Lead 1", "Lead 2" and"Return". Signal current flows in or out of "Lead 1" and return current flows on the "Return" lead. Mutualinductance between signal and return lead significantly affects the performance of the signal loop.Therefore, mutual inductance of all leads to the ground lead must be included in detailed simulations.Similarly for calculating package cross-talk, mutual inductance between two signal leads should be takeninto account. Package circuit models can be provided in SPICE format. For package SPICE modelscontact your local National Semiconductor technical representative.Figure 2. Equivalent of three package leads3Example R-L-C Values for PackagesThis section provides RLC values for National's packages. The following is true for the data presented inthis note:1. Example R-L-C data is provided for typical leads only. For detailed analysis, accurate package modelsSNOA405A – May 2004 – Revised May 2004Submit Documentation FeedbackAN-1205 Electrical Performance of PackagesCopyright 2004, Texas Instruments Incorporated3

Example R-L-C Values for Packages2.3.4.5.6.www.ti.comshould be obtained.The PC board plane is assumed 20 mils (0.5 mm) below the seating plane of the package.Wirebond parasitics are not included in this section; they are separately provided in Table 7.Inductance given is partial AC inductance; it does not scale linearly with length.Resistance provided is AC resistance calculated at 1GHz.Mutual inductance to the immediate (M12) and the next-of-immediate (M13) leads is provided. It shouldbe noted that in packages with no power planes, significant mutual coupling exists beyond these. Forexample for a PQFP, the coupling coefficient (k) between two leads that are separated by 10 leads canbe as high as 0.3.Table 2. Example RLC values for lead-frame based packages and micro SMDPackageQFPBodySize(mm)R (ohm)LeadCountL (nH)M (nH)CorneCorneCenterCenterrrC (pF)CornerCenterM12M13M12M13CM12 (pF)CorneCorneCenterCenterrr28 00.6020 2012 .044.43.221.51.51.10.350.250.60.45SSOP5.3 DIP19 2-(1)MicroSMD(largebump)(1)(1)3.1Micro SMD package does not have wirebonds.LAMINATE BASED CSP (CHIP-SCALE PACKAGE)There are two types of laminate based CSPs: single row and dual row. Because the lead-geometry of allsingle row CSPs is the same, the RLC parasitics are the same. However, for the dual row CSPs, there arethree types of lead geometries (labeled as #1, #2 and #3 in Table 3), and the parasitics are different fordifferent geometries. To determine which dual row design is being used for your product, please contactyour local National Semiconductor technical representative. Figure 3 shows a picture of a typical singleand dual row CSP. Table 3 gives typical RLC characteristics of CSPs. Mutual inductance terms in thecolumns in Table 3 are illustrated in Figure 3. M12 is the mutual inductance between two neighboringleads in the same (inner or outer) row. MRR is the mutual inductance between the neighboring leads ofdifferent rows. For more details on the construction of CSP packages, browse tohttp://www.national.com/packaging.4AN-1205 Electrical Performance of PackagesCopyright 2004, Texas Instruments IncorporatedSNOA405A – May 2004 – Revised May 2004Submit Documentation Feedback

Example R-L-C Values for Packageswww.ti.comFigure 3. Laminate CSP packages (not to scale)Table 3. Example RLC data for CSP packagesR (ohm)PackageL (nH)M (nH)OuterInnerOuterInnerM12OuterInnerC (pF)MRROuterInnerCM (pF)Dualrow, #1128 w/inlinebondpads #2128 w/inlinebondpads #3128 3Singlerow3.2LeadCount0.400.100.080.07BGA PACKAGESA typical BGA (ball grid array) package is shown in Figure 4. Each side of the package has four rows ofsolder-balls. The traces going to the solder balls in the corners of the package are significantly longer,therefore the data is grouped by "corner" and "center" leads. In Table 4, "O" column gives data for theoutermost row of solder-balls on the package (as illustrated in Figure 4); similarly, "I" column gives data forthe innermost row of solder balls on the package. LBGAs and FBGAs (low-profile BGAs and fine-pitchBGAs, respectively) are often custom routed, and it is therefore difficult to provide generalized R-L-C data.Data for an LBGA and an FBGA is provided for reference.SNOA405A – May 2004 – Revised May 2004Submit Documentation FeedbackAN-1205 Electrical Performance of PackagesCopyright 2004, Texas Instruments Incorporated5