Wafer Bonding Technology FOR VACUUM PACKAGING USING GOLDSILICON EUTECTICincluding adhesive, glass frit, solder, eutectic, siliconfusion/direct and anodic bonding have been used. Ofthese, eutectic bonding is one of the most attractivebecause it is easy to use, it forms a soft eutectic to allowbonding over non-planar surfaces, it can be done atslightly above the eutectic temperature (363 C), and itdoes not out-gas as some of the approaches.Although Au-Si eutectic has long been used for waferbonding and packaging [1, 7], few have reported itssuccessful use in vacuum packaging. There are severalreasons for this, including non-uniform eutectic flow,void formation, insufficient eutectic material in betweenwafers causing non-uniform bonding, oxidation of bondsurfaces, and poor surface contact/adhesion.Furthermore, few published reports have presented datashowing full wafer-level bonding [2]. The mainproblem with Au-Si eutectic bonding has been a lack ofuniformity over an entire wafer and lack ofreproducibility from wafer to wafer and temperatureconsistency. This paper presents a uniform, high-yield,reproducible, silicon-gold eutectic wafer-level bondingtechnology used for vacuum encapsulation of MEMS.The paper presents a detailed description of the bondingprocess and the steps necessary to ensure a uniform andreproducible bond.The vacuum inside packagedcavities is monitored using a thin flexible diaphragmthat is fabricated on one side of the packaged cavity andmeasured using Pirani gauge fabricated in the devicewafer. This wafer-level bonding technology can beapplied to a variety of MEMS devices which require aprescribed level of vacuum or pressure, excellentbonding strength, low fabrication cost, and highreliability and yield with no stress due to the similarmaterial being used for the device and cap wafer.Abstract— In this paper successful silicon waferbonding technology using gold-silicon eutectic isreported. The wafers, device wafer and cap wafer arebonded in vacuum. Device wafer is terminated on thesurface with a bond layer that can be single crystalsilicon, a layer of polysilicon, gold or any other suitablemetal, dielectric or semiconductor layer, and the capwafer contains an electroplated gold bond ring. Bondinghas been carried out in a standard wafer bonder byperforming a pre-bake at 300 C and then pressing thewafers together by 1Mpa and subsequent bonding at atemperature of about 400 C for 30 minutes. Bondingyield of more than 95% is achieved on 4” silicon waferswith excellent reproducibility. Excellent coverage ofsoft eutectic bonding over non-planar surfaces has beeninvestigated using 1.2mm-thick insulated feedthroughsof polysilicon, which shows a good flow of eutecticmaterial over the feedthroughs. Thin film polysilicondiaphragm ( 2.5mm-thick) and micro-Pirani gauge havebeen used to monitor and measure the low-pressureinside the packaged vacuum cavity. It is more than oneyear that we are monitoring the pressure by the amountof buckling in the diaphragm, and so far no pressuredrop is observed. Direct pressure measurement is alsounderway by the vacuum packaged floating Piranigauges fabricated inside the device wafer. It also hasbeen shown that polysilicon is a better source materialin gold- silicon eutectic formation as it bonds atrelatively lower temperature than single crystal silicon.1. IntroductionLow-cost, simple, and reproducible hermetic/vacuumpackaging technologies are required for manymicrosystems, including biosensors, resonant devicesand RF MEMS. Several groups, including ours, havebeen developing new techniques for implementing smallpackages bonding [1-6]. Most of these involve bondingof two wafers, a package (cap) silicon/glass wafer, and adevice silicon wafer. Several wafer bonding techniques,2. Eutectic BondingThere are different methods of bonding; eutecticbonding is the most promising one due to the soft natureof the material in the eutectic phase. Among different27Journal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004Yuhai MeiJ.S. MitchellG. Roientan Lahiji1and Khalil NajafiCenter for Wireless Integrated Microsystems, The University of Michigan1301 Beal Ave., Ann Arbor, MI 48109, USA1Iran University of Science and Technology, Namak, Tehran, Iran١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ Archive of SID

mechanical characteristics.In the following, thefabrication process for each of these wafers is firstdescribed, and the details of wafer bonding process arepresented.elements, gold-silicon and aluminum-silicon are the bestsystem from both scientific and practical point of views[8]. Gold-silicon system has one of the simplest eutecticphase diagrams and eutectic formation occurs at 363 Cfor 19 at % Si, as shown in the phase diagram in Fig. 1.The gold-silicon eutectic can be used to bond twosilicon wafers, and it has the great potential to be usedfor hermetic and vacuum packaging. To form theeutectic, suitable amount of silicon and gold have to beprovided to the interface where two wafers are bonded.Typically, the gold is deposited on one of the wafers to adesired thickness, and the silicon is provided either fromthe bulk of one of the wafers, or from thin filmsdeposited on one or both wafers. Figure 2, for example,shows two wafers, the device wafer containingfeedthroughs and a top poysilicon layer, and the capwafer containing a package cavity and an electroplatedgold bond ring. When the two wafers are brought intointimate contact and heated to above 363 C, silicon issupplied from both the cap wafer (underneath the goldring) and the device wafer (the polysilicon layer), andwill react with gold to initiate the eutectic liquidformation. Upon cooling, the bond consists of Au-Sihypereutectic phase and represents a typical strongdiffusion bond [6]. We will present additional detailand discussion on the bonding mechanisms, anddifferent bond interfaces and materials later in the paper.Fig. 2: Schematic diagram of Au-Si eutecticbonding: at (a) room temperature, (b) 363 C.Figure 3 shows the fabrication process of the capwafer. Thermal oxide (0.5mm) is first deposited on thebackside of the cap wafer in order to protect the waferduring the following KOH wet etching process. Next,the bonding layer is formed on the front surface. Itconsists of a layer of Ti (200Å), followed by a seedlayer of Au (1000Å), and a top layer of Cr (500Å). Thechromium is patterned in areas where the thick goldbond ring is to be formed. The bond ring width istypically 200mm. Gold is now electroplated to athickness of 4-8mm through a thick photoresist mask.The plating mask and the underlying Ti/Au/Cr layer arenow removed and the wafer is etched in KOH for 60minutes to form a 50mm deep recess to create thepackage cavity. This completes the processing of thecap wafer.Figure 4 shows the fabrication process of the devicewafer. In the early experiments, the device wafersimply supports a multi-layer of thin dielectric andpolysilicon films. These films eventually form a thindiaphragm that can later be used to monitor the pressureinside the package. Thermal oxide (2mm) and LPCVDSi3N4 (1800Å) and SiO2 (2300Å) are first deposited on asilicon substrate for electrical insulation followed by thedeposition of 1.2mm LPCVD polysilicon. Thepolysilicon is then phosphorus-doped and can bepatterned to form electrical interconnects and3. Fabrication processesJournal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004To develop and characterize the bonding process, aset of test wafers and devices were fabricated. Theexperiments involved two wafers, a device wafer whichsupports the required bonding layers, and a silicon capwafer that contains the gold bond ring and the packageFig. 1: Binary phase diagram of Au-Si alloy.cavity. Silicon is used as the cap wafer because it canbe easily machined, matches the thermal expansion ofthe device wafer, is low cost, and has excellent١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ 28Archive of SID

solidification.feedthroughs. In order to prevent the diffusion of Auinto this interconnect layer during the bonding process,an LPCVD SiO2 (2300Å)/ Si3N4 (1800Å) barrier layer isdeposited. Next, a second layer of LPCVD polysilicon(0.5mm) is deposited; this polysilicon film forms thebonding layer on the device wafer. The wafers are nowready to be bonded. Note that the diaphragms arereleased after the two wafers are bonded together.Diaphragm release is performed by etching the devicewafer from the backside in a DRIE as illustrated in Fig.4(b).4. Experimental resultsAs stated above, the diaphragms are released in aDRIE etcher after the wafers are bonded together.Figure 5(a) shows the photograph of a full bonded waferpair. Inspection of the wafer shows a yield of more than95% of the packaged diaphragmsdeflecting down across the wafer. Figures 5(b, c)show close-ups of the buckled diaphragms over thevacuum-sealed cavity. Note that the thin diaphragmbends by a large amount and still survives the 1atmosphere of pressure difference across it. Figure 6shows a SEM photograph of the cleaved bond interface,showing the eutectic region. Figure 7 shows thephotograph of a device where the cap wafer is forcefullybroken and removed, leaving behind silicon in the bondareas. This illustrates a very uniform and strong bond.The pressure in the sealed cavity can be grosslymonitored by monitoring the deflection of thediaphragm as a function of pressure and time. When thebonded wafer is placed inside a vacuum chamber, thediaphragms begin to move as the chamber is pumpeddown and the differential pressure across the diaphragmdecreases. Several wafers have been bonded and testedin this fashion. The longest wafer has been tested formore than one year and the diaphragms are stilldeflected in ambient pressure. The above technique isnot the most accurate to measure and monitor thepressure inside the cavity. To do this, one needsvacuum sensors. Therefore other set of experiments,which includes integrated vacuum pressure sensor, hasbeen packaged using the above eutectic method. Piranigauges which has already been developed [9], isfabricated in the device wafer and is packaged usinggold-silicon eutectic in order to measure the pressureinside the cavity. This allows us to directly measure thepackage pressure down to the 10 mTorr range. Fig.8(a)shows the SEM photograph of a packaged Pirani gauge,where the cap wafer has been forcefully removed. TheFig. 3: Fabrication process flow of silicon cap wafer.The cap and device wafers are now aligned, and thenbonded. The most critical step in the process is theexact bonding sequence. Bonding is performed in anElectronic Vision EV-420 bonder, where thetemperature and pressure can be controlled. Afterplacement in the bonding chamber, the chamber ispumped down to a vacuum level of about 0.25mTorr.The wafers are then baked at 300 C for about 60minutes to bake out any residual materials off of thesurfaces of the package cavity. Note that this baking isperformed at 300 C, which is far below the eutecticpoint. The wafers are now brought into intimate contactunder an applied pressure of 1MPa, and the wafer stackis heated to the desired bonding temperature. Most ofour bonds were performed at a temperature of 400 C forabout 20-30 minutes. The applied pressure helps todistribute the eutectic material throughout the bondinterface. Now, the wafers are cooled down to roomtemperature and removed from the bonder. It is worthnoting that it is desirable to rapidly cool down the waferstack after bonding in order to obtain a finemicrostructure for the gold-silicon alloy after29Journal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004Fig. 4: Process flow of the device wafer,containing a 2.52mm multilayer diaphragm usedfor vacuum monitoring.١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ Archive of SID

diffuse through the Au layer and reach the interface,thus forming strong chemical bonds at the interface ofAu and polysilicon. Although in some regions, Auatoms arrive at the interface, the strong bond betweenSi-Si is not be affected (Fig. 11(b)) therefore there stillremain a large number of Si-Si bonds along theinterface. Consequently a very strong and uniform bondestablishes across the entire interface. The abovemechanisms can also be applied to both nitride andpoly/nitride.pressure sensitivity of the gauge is also depicted inFigure 8(b).In addition to bonding cap wafers to flat devicewafers without any feedthroughs, we have also bondedthe cap wafer to a device wafer with 1.2mm thickfeedthroughs. As previously mentioned, the advantageof the eutectic is that it flows over these feedthroughs.The wafers bonded with these feedthroughs also showexcellent uniformity and reproducibility. Figs. 9a,bshows an excellent coverage of the bond overfeedthroughs in the device wafers.5. DiscussionJournal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004In order to characterize and understand the waferboning process, we have also bonded many differentwafers with a different set of materials and bondinglayers. The material sets, which were bonded andtested, included: Si/Ti/Au to Au/Ti/Si; Si/Ti/Au tosingle crystal Si; Si/Ti/Au to PolySi/Si; Si/Ti/Au toOxide/Si; and Si/Ti/Au to Nitirde/Si. Of these wafers,we have found that the bond quality and uniformitybetween Au-Au, Au-Si, and Au-PolySi is the best. Inparticular, it is noted that the bond quality is best whenthe gold and silicon are supplied from the two wafers,instead of both from the same wafer. Test wafers wherethe Au-Si eutectic was bonded to a substrate coveredwith either oxide or nitride produced very non-uniformand poor bonds. The reasons for this are not exactlyknown at this point, but the following discussionexplains what we believe is occurring in the bondingprocess.To help illustrate this, we refer to Figure 10. Let’sconsider the case of a cap wafer with a gold-siliconeutectic ring being bonded to a silicon oxide surface.The surface of the oxide is generally terminated by -OHgroups. During eutectic bonding, silicon atoms from thecap wafer diffuse through the gold layer, and arrive atthe top surface of the oxide, where they either establisha weak chemical bond with -H, or react with -OHgroups to form a Si-O bond. This results in thegeneration of hydrogen, which in turn forms micro- ornano- voids along the bond interface. These are thecause of a weak bond between the eutectic alloy and theoxide.If LPCVD polysilicon or silicon is used as bondingmaterial on the device wafer, a strong bond is obtained.The polysilicon layer is deposited immediately after thedeposition of a LPCVD oxide layer on the device wafer;a strong chemical bond exists between silicon andoxygen atoms along the interface between the oxide andthe polysilicon (Fig. 11(a)). When the surface of thepolysilicon (Si) is exposed to air and water, a layer of OH group forms on the surface (Fig. 11(a)). A very thinlayer of oxide is also formed. This very thin nativeoxide and -OH layers are consumed by Si atoms that١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ (a)(b)(c)Fig. 5: (a) Photograph of two bonded Si wafers withcavities covered by thin diaphragms. The yield is 95%.(b) Close-up view of some of the vacuum sealed cavities,showing buckled diaphragms.(c) Close-up with of a buckled diaphragm covering a sealedcavity. The diaphragm has buckled down by 28mm.30Archive of SID

We have also studied the effect of the cooling rate onthe quality of the eutectic bond. It is well-known thatthe physical properties of a metal alloy, such as gasdiffusivity, depends on the microstructure whichdepends on such variables as the alloying elementspresent, their concentrations, and the heat treatment ofthe alloy. As shown in Fig. 1, at 363 C, the Au-Sialloy is completely liquid (of composition 19% Si). Atthe eutectic point, the solidification process starts andsolids of Au and Si begin to form. For packagingapplications, one needs a fine and uniformmicrostructure in the alloy because smaller grains canreduce the gas diffusion through the structure. Fastcooling (quenching) of the eutectic results in a finemicrostrucrture, and is therefore preferred. We haveanalyzed the microstructure of both quenched andslowly-cooled Au-Si eutectic, and observed that thequenched eutectic has a finer microstructure.(a)1.150Voltage (Volt)1.1451.1401.1351.1301.1251.1201.1151.11010 -5 10 -4 10 -3 10 -2 10 -1 10 010 110 210 3Pressure (Torr)(b)Fig. 6: SEM of cross-section of the bond interface.(a)(b)Fig. 9: (a) Vacuum packages formed on a 4” siliconwafer. (b) Close-up view of one of the siliconpackages, showing bonding pads, and feedthroughs.Fig. 7: SEM photograph of broken bond regionshowing excellent uniformity.31Journal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004Fig.8: (a) The SEM photograph of encapsulated Piranigauge after the silicon cap is forcefully broken away.(b): Measured performance of the Pirani gauge showingpressure in the range of 0.01-10 Torr can be measured.١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ Archive of SID

been tested by monitoring the deflection of thin flexiblediaphragms covering the sealed cavities and directmeasurement of the pressure inside the cavity usingintegrated Pirani gauge, which show stable pressureinside the sealed cavity after almost more than a year.The above proposed Au-Si eutectic bondingexperiments indicate that the Au-Si eutectic bond mustbe conducted: (a) in a vacuum or inert gas ambient toavoid further oxidization at high temperature; (b)LPCVD polysilicon must be deposited immediately afterLPCVD oxide deposition to achieve a clean and stronginterface between silicon and oxide; (c) some contactforce must be applied on the wafers to provide anintimate contact between the bonding materials of Auand polysilicon, (d) the bonded wafers should be cooleddown as fast as possible around the eutectic temperature;(e) In order to provide sufficient Au-Si eutectic, thethickness of the eutectic material should be severalmicrons so when the wafers are pressed together,eutectic can cover over non-planar surfaces; and (f) thewafers should be properly baked to minimize outgassing.AcknowledgementsThe authors acknowledge the support of IntegratedSensing Inc. (ISSYS) for wafer testing. This research issupported by the Engineering Research Centers, aprogram of the National Science Foundation underAward Number EEC-9986866.References[1] M .B. Cohn, K. F. Bohringer, J. M. Noworolski, A.Singh, C. G. Keller, K. Y. Goldberg, R. T. Howe,“Microassembly Technologies for MEMS”, Proceedingof SPIE, 3512 (1998), pp. 2 16.[2] F. Ohara, et al., “Method for Manufacturing aSemiconductor Acceleration Sensor Device,” U.S.Patent 5668033, 1997.[3] Y. Mei, G. R. Lahiji, and K. Najafi, “A Robust GoldSilicon Eutectic Wafer Bonding Technology for VacuumPackaging,” A Solid-State Sensor, Actuator, andMicrosystems Workshop, Hilton Head, June, 2002.[4] B. Ziaie, J. A. V. Arx, M.R. Dokmeci, and K. Najafi,“A Hermetic Glass-Silicon Micropackage with HighDensity On-Chip Feedthroughs for Sensors &Actuators”, JMEMS, Vol. 5, No. 3, September (1996),pp. 166-179.4.Fig. 10: Schematic drawing of atomic configurations atbonding interfaces with LPCVD oxide only.Journal of Iranian Association of Electrical and Electronics Engineers - Vol.1 - No.2 - Summer & Fall 2004[5] Y. T. Cheng, W.T. Hsu, Liwei Lin, C.T. Nguyen, andK. Najafi, “Vacuum Packaging Technology UsingLocalized Aluminum/Silicon-To-Glass Bonding”,MEMS 2001, Interlaken, Switzerland, Jan. (2001),pp.18-21.[6] R. K. Shukla and N.P. Mencinger, “A CriticalReview of VLSI Die-Attachment in High ReliabilityApplications”, Solid State Technology, July (1985), pp.67-74.Fig. 11: Schematic drawing of atomic configurations atbonding interfaces with LPCVD oxide and polysilicon.[7] R.F. Wolffenbuttel, “Low-Temperature IntermediateAu-Si Wafer Bonding: Eutectic or Silicide Bond”,Sensors and Actuators, A-62 (1997), pp. 680-686.6. ConclusionWe have successfully demonstrated a uniform, highyield, reproducible, silicon-gold eutectic wafer-levelbonding technology and its application to MEMSvacuum packaging. Uniform bonding has been achievedacross 4” silicon wafers with better than 95% yield onboth flat wafers and wafers with feedthroughs. The bestbonds are achieved on wafer pairs where the cap wafer ismade of silicon with an electroplated layer of gold, and adevice wafer with a polysilicon bond ring deposited overinsulated feedthroughs. Vacuum-sealed cavities have١٣٨٣ ﻣﺠﻠﻪ ﺍﻧﺠﻤﻦ ﻣﻬﻨﺪﺳﻴﻦ ﺑﺮﻕ ﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺍﻳﺮﺍﻥ‐ ﺳﺎﻝ ﺍﻭﻝ‐ ﺷﻤﺎﺭﻩ ﺩﻭﻡ‐ ﺗﺎﺑﺴﺘﺎﻥ ﻭ ﭘﺎﻳﻴﺰ [8] B. Bokhonov, M. Korchagin, “ In situ investigationof Stage of the formation of eutectic alloys in Si-Au andSi-Al System”, Journal of Alloys and Compounds 312(2000), 238-250.[9] J. Chae, B. Stark, and K. Najafi, “ A MicromachinedPirani Gauge with Dual Heat Sink,” The Proceedings ofthe 17th IEEE International Conference on Micro ElectroMechanical Systems (MEM 2004), Maastricht,Netherlands, January 2004.32Archive of SID

Abstract— In this paper successful silicon wafer bonding technology using gold-silicon eutectic is reported. The wafers, device wafer and cap wafer are bonded in vacuum. Device wafer is terminated on the surface with a bond layer that can be single crystal silicon, a layer of polysilicon, gold or any other suitable