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UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20226.4 Thermal InformationUCC27282THERMALMETRIC(1)D8 PINSDRCDRMDPRUNIT10 PINS 8 PINS 10 PINSRθJAJunction-to-ambient thermal resistance118.347.3TBDTBD C/WRθJunction-to-case (top) thermal resistance53.650.3TBDTBD C/WRθJBJunction-to-board thermal resistance63.121.3TBDTBD C/WψJTJunction-to-top characterization parameter10.71.0TBDTBD C/WψJBJunction-to-board characterization parameter62.121.2TBDTBD C/WRθJunction-to-case (bottom) thermal resistancen/a4.4TBDTBD C/WJC(top)JC(bot)(1)For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.6.5 Electrical CharacteristicsVDD VHB VEN 12 V, VHS VSS 0 V, No load on LO or HO, TJ –40 C to 140 C, (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAX UNITSUPPLY CURRENTSIDDVDD quiescent currentVLI VHI 00.30.4mAIDDOVDD operating currentf 500 kHz, CLOAD 02.24.5mAIHBHB quiescent currentVLI VHI 0 V0.20.4mAIHBOHB operating currentf 500 kHz, CLOAD 02.54mAIHBSHB to VSS quiescent currentVHS VHB 100 V5.050IHBSOHB to VSS operating current(1)f 500 kHz, CLOAD 00.1mAIDD DISIDD when driver is disabledVEN 07.0μAμAINPUTVHITInput rising threshold1.92.12.4VVLITInput falling threshold0.91.11.3VVIHYSInput voltage HysteresisRINInput pulldown e threshold on EN pin to enable the driverVDISVoltage threshold on EN pin to disable the driverVENHYSEnable pin Hysteresis0.3VRENEN pin internal pull-down resistor250kΩTENTime to enable the driver once the EN pin ispulled highVEN 2V18μsTDISTime to disable the driver once the EN pin ispulled lowVEN 0V1.5μs0.71.21VUNDERVOLTAGE LOCKOUT PROTECTION (UVLO)VDDRVDD rising threshold4.75.05.4VVDDFVDD falling threshold4.24.54.9VVDDHYSVDD threshold hysteresisVHBRHB rising threshold with respect to HS pin3.33.74.4VVHBFHB falling threshold with respect to HS pin3.03.34.1VVHBHYSHB threshold hysteresis0.5V0.3Submit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282V5

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20226.5 Electrical Characteristics (continued)VDD VHB VEN 12 V, VHS VSS 0 V, No load on LO or HO, TJ –40 C to 140 C, (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAX UNITBOOTSTRAP DIODEVFLow-current forward voltageIVDD-HB 100 μA0.550.85VVFIHigh-current forward voltageIVDD-HB 80 mA0.881.0VRDDynamic resistance, ΔVF/ΔIIVDD-HB 100 mA and 80 mA1.52.5ΩLO GATE DRIVERVLOLLow level output voltageILO 100 mA0.0850.4VVLOHHigh level output voltageILO -100 mA, VLOH VDD – VLO0.130.42VVLO 0 V3.0AVLO 12 V3.0APeak pullup current(1)Peak pulldown current (1)HO GATE DRIVERVHOLLow level output voltageIHO 100 mA0.10.4VVHOHHigh level output voltageIHO –100 mA, VHOH VHB- VHO0.130.42VPeak pullup current (1)VHO 0 V3.0AVHO 12 V3.0A(1)Peak pulldown current(1)Parameter not tested in production6.6 Switching CharacteristicsVDD VHB 12 V, VHS VSS 0 V, No load on LO or HO, TJ –40 C to 140 C, (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITPROPAGATION DELAYStDLFFVLI falling to VLO fallingSee Section 6.71630nstDHFFVHI falling to VHO fallingSee Section 6.71630nstDLRRVLI rising to VLO risingSee Section 6.71630nstDHRRVHI rising to VHO risingSee Section 6.71630nsDELAY MATCHINGtMONFrom LO being ON to HO being OFFSee Section 6.717nstMOFFFrom LO being OFF to HO being ONSee Section 6.717nsOUTPUT RISE AND FALL TIMEtRLO, HO rise timeCLOAD 1800 pF, 10% to 90%12nstFLO, HO fall timeCLOAD 1800 pF, 90% to 10%10nstRLO, HO (3 V to 9 V) rise timeCLOAD 0.1 μF, 30% to 70%0.330.6μstFLO, HO (3 V to 9 V) fall timeCLOAD 0.1 μF, 70% to 30%0.230.6μsMISCELLANEOUSTPW,minMinimum input pulse width that changes the outputBootstrap diode turnoff(1)6time(1)IF 20 mA, IREV 0.5 A20ns50nsParameter not tested in productionSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20226.7 Timing DiagramsLIVoltage (V)Voltage (V)HIInput(HI, LI)LOTDLRR, TDHRROutput(HO, LO)HOTime (s)TDLFF,TDHFFTime (s)TMOFFTMON6.8 Typical CharacteristicsUnless otherwise specified VVDD VHB 12 V, VHS VVSS 0 V, No load on V0.120.1-40A.HB Quiescent Current (mA)VDD Quiescent Current (mA)0.28-20020406080Temperature ( A.VHI VLI 0 VFigure 6-1. VDD Quiescent Current020406080Temperature ( C)100120140IHBQVHI VLI 0 VFigure 6-2. HB Quiescent CurrentSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC272827

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20224.56-40 C25 C140 C53.53IHBO (mA)4IDDO (mA)-40 C25 C140 C432.521.52110.500123 4 5 67 10A.20 30 50 70100Frequency (kHz)CL 0 F2001500 10003 4 5 67 10A.VDD VHB 12V20 30 50 70100Frequency (kHz)CL 0 F200500 1000IHBOVDD VHB 12VFigure 6-4. HB Operating CurrentFigure 6-3. VDD Operating Current14205.5V12V16V1218161014IHBS (PA)IDD DIS (PA)2IDDO8612108644220-40-20A.020406080Temperature ( C)CL 0 F1001200-40140A.VEN 0 V20406080Temperature ( C)100120140IHBSFigure 6-6. HB to VSS Quiescent Current2.221.1452.2151.142.21Input Falling Threshold (V)Input Rising Threshold (V)0VHB VHS 100VFigure 6-5. VDD Current When .172.165-40-20020406080Temperature ( 105-40IN RFigure 6-7. Input Rising Threshold8-20IDD-20020406080Temperature ( C)100120140IN FFigure 6-8. Input Falling ThresholdSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20222801.755.5V12V16V1.71.65Enable Threshold (V)Input Resistance -20020406080Temperature ( C)1001201.2-40140020406080Temperature ( C)100120140EN TFigure 6-10. Enable ThresholdFigure 6-9. Input Pull-down e Delay (Ps)Disable Threshold (V)-20R 06080Temperature ( C)10012015-40140-20Figure 6-11. Disable Threshold2.1406080Temperature ( C)100120140T ENFigure 6-12. Enable Delay5.5V12V16V52.052VDD UVLO (V)Disable Delay RiseFall1.651.6-40-20020406080Temperature ( C)100Figure 6-13. Disable Delay1201404.2-40-20T Di020406080Temperature ( C)100120140VDDUFigure 6-14. VDD UVLO ThresholdSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC272829

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20224Diode Forward Voltage (V)HB UVLO (V)3.83.63.43.2RiseFall3-40-20020406080Temperature ( C)100120140HBUVFigure 6-15. HB UVLO Threshold1.8Output Voltage (V)Diode Dynamic Resistance 80Temperature ( C)100120100uA80mA-20020406080Temperature ( C)100120140VfFigure 6-16. Boot Diode Forward Voltage 6V-20020406080Temperature ( C)100120140V LOR DyIO 100mAFigure 6-17. Boot Diode Dynamic ResistanceFigure 6-18. LO Low Output Voltage (VLOL)0.210.20.18Output Voltage (V)Output Voltage 0-20020406080Temperature ( C)1001201405.5V12V16V-200V LO20406080Temperature ( C)100120140UCC2V HOIO 100mAIO -100mAFigure 6-19. LO High Output Voltage .110.1050.10.0950.090.085-40Figure 6-20. HO Low Output Voltage (VHOL)Submit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20220.19150.1814.5140.16LO Rise Time (ns)Output Voltage (V)0.170.150.140.130.120.11-20020406080Temperature ( 5.5V12V16V109.5-40140-20IO -100mA100120140LO R185.5V12V16V5.5V12V16V159.6HO Rise Time (ns)LO Fall Time (ns)406080Temperature ( C)Figure 6-22. LO Rise Time10.29.820CL 1800pFFigure 6-21. HO High Output Voltage (VHOH)100V e ( C)1001206-40140-20CL 1800pF120140HO R0.380.360.34Time (Ps)HO Fall Time 247.40.227.2-40406080Temperature ( C)Figure 6-24. HO Rise Time98.620CL 1800pFFigure 6-23. LO Fall Time8.80LO F-20020406080Temperature ( C)100CL 1800pFFigure 6-25. HO Fall Time1201400.2-40RiseFall-20020406080Temperature ( C)100HO F120140LO RCL 100nFFigure 6-26. LO Rise & Fall TimeSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC2728211

5Time (ns)Time (Ps)SNVSAQ5B – NOVEMBER 2018 – REVISED MAY ll0.20.175-40-20020406080Temperature ( C)10012014.5-40140020406080Temperature ( C)100120140TDHRCL No LoadFigure 6-27. HO Rise & Fall TimeFigure 6-28. HO Rising Propagation Delay (TDHRR)2019.51918.5Time (ns)Time (ns)-20HO RCL mperature ( C)1001205.5V12V16V15.514015-40-20020TDHFCL No Load406080Temperature ( C)100120140TDLRCL No LoadFigure 6-29. HO Falling Propagation Delay (TDHFF) Figure 6-30. LO Rising Propagation Delay (TDLRR)1918.518Time 0Temperature ( C)100120140TDLFCL No LoadFigure 6-31. LO Falling Propagation Delay (TDLFF)12Submit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20227 Detailed Description7.1 OverviewThe UCC27282 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channelFETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled withtwo TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as longas signals meet turn-on and turn-off threshold specifications of the UCC27282. The floating high-side driver iscapable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated inthe UCC27282 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at highspeed while consuming low power and provides clean level transitions from the control logic to the high-sidegate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. ENpin is provided (in DRC packaged parts) to enable or disable the driver. The driver also has input interlockfunctionality, which shuts off both the outputs when the two inputs overlap.7.2 Functional Block RIVERSTAGELOInterlock LogicVSSLICopyright 2018, Texas Instruments IncorporatedSubmit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC2728213

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20227.3 Feature Description7.3.1 EnableThe device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltageis above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground.An internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables thedevice. Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it isrecommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor isrecommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filtercapacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analogor a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresishelps prevent any nuisance tripping or chattering of the outputs.7.3.2 Start-up and UVLOBoth the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supplyvoltage (VDD) and the bootstrap capacitor voltage (VHB–HS). The UVLO circuit inhibits each output until sufficientsupply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chatteringduring supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both theoutputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrapcapacitor (VHB–HS) disables only the high- side output (HO).Table 7-1. VDD UVLO Logic OperationCondition (VHB-HS VHBR and VEN Enable Threshold)VDD-VSS VDDR during device start-upVDD-VSS VDDR – VDDH after device LIHOLOHLLLLHLHHHLLLLLLHLLLLHLHHHLLLLLLTable 7-2. HB UVLO Logic OperationCondition (VDD VDDR and VEN Enable Threshold)VHB-HS VHBR during device start-upVHB-HS VHBR – VHBH after device start-up7.3.3 Input Stages and InterlockThe two inputs operate independently, with an exception that both outputs will be pulled low when both inputsare high or overlap. The independence allows for full control of two outputs compared to the gate drivers thathave a single input. The device has input interlock or cross-conduction protection. Whenever both the inputs arehigh, the internal logic turns both the outputs off. Once the device is in shoot-through mode, when one of theinputs goes low, the outputs follow the input logic. There is no other fixed time de-glitch filter implemented in thedevice and therefore propagation delay and delay matching are not sacrificed. In other words, there is no built-indead-time due to the interlock feature. Any noise on the input that could cause the output to shoot-through willbe filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,14Submit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC27282

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 2022they can be connected to outputs of either digital controller or analog controller. Inputs can accept wide slewrate signals and input can withstand negative voltage to increase the robustness. Small filter at the inputs ofthe driver further improves system robustness in noise prone applications. The inputs have internal pull downresistors with typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.HILILOInterlockHOTimeFigure 7-1. Interlock or Input Shoot-through Protection7.3.4 Level ShifterThe level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-sidedriver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO outputwhich is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible andtherefore the device provides excellent propagation delay characteristic and delay matching with the low-sidedriver output. Low delay matching allows power stages to operate with less dead time. The reduction in deadtime is very important in applications where high efficiency is required.7.3.5 Output StageThe output stages are the interface from level shifter output to the power MOSFETs in the power train. High slewrate, low resistance, and high peak current capability of both outputs allow for efficient switching of the powerMOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The deviceoutput stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can alsosustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers thehighest peak source current when it is most needed, during the Miller plateau region of the power switch turn ontransition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.Submit Document FeedbackCopyright 2022 Texas Instruments IncorporatedProduct Folder Links: UCC2728215

UCC27282www.ti.comSNVSAQ5B – NOVEMBER 2018 – REVISED MAY 20227.3.6 Negative Voltage TransientsIn most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground.In some situations, board capacitances and inductances can cause the HS node to transiently swing severalvolts below ground, before the body diode of the external low-side MOSFET clamps this swing. When used inconjunction with the UCC27282, the HS node can swing below ground as long as specifications are not violatedand conditions mentioned in this section are followed.HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions canactivate parasitic transistors which may result in excessive current flow from the HB supply. This may result indamage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can beplaced externally between HO and HS or LO and VSS to protect the device from this type of transient. The diodemust be placed as close to the device pins as possible in order to be effective.Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V,then VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally whenHS swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantlyovershoot.Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gatedriver device. The capacitor should be located at the leads of the device to minimize series inductance. Thepeak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causesvoltage ringing at the leads of the device which must be avoided for reliable operation.Based on application board design and other operating parameters, along with HS pin, other pins such as inputs,HI and LI, might also transiently swing below ground. To accommodate such operating conditions UCC27282input pins are capable of handling absolute maximum of -5V. As explained earlier, based on the layout and otherdesign constraints, some times

MOSFETs with minimum switching losses during the transition of the MOSFET Miller plateau. Since the inputs are independent of the supply voltage, UCC27282 can be used in conjunction with both analog and digital controllers. The input pins as well as the HS pin are able to tolerate significant negative voltage, which improves system robustness.