mopdf.com

CP21053. Pinout and Package DefinitionsTable 7. CP2105 Pin DefinitionsNamePin #VDD6TypeDescriptionPower In Power Supply Voltage Input.Power Out Voltage Regulator Output. See Section 10.VIO5GND2RST9REGIN7VBUS8D InVBUS Sense Input. This pin should be connected to the VBUS signal of aUSB network.D 3D I/OUSB D D–4D I/OUSB D–SUSPEND1*D OutIn GPIO mode, this pin indicates whether the device is in the USB Suspend ornot. The polarity can be configured via the configuration PROM, and defaultsto active-low.D InIn modem control mode, this pin is the Ring Indicator control input (active low)for the Standard Comm Interface.D I/OIn GPIO mode, this pin is a user-configurable input or output for the StandardComm Interface.D InIn modem control mode, this pin is the Data Carrier Detect control input(active low) for the Standard Comm Interface.D I/OIn GPIO mode, this pin is a user-configurable input or output for the StandardComm Interface.D OutIn modem control mode, this pin is the Data Terminal Ready control output(active low) for the Standard Comm Interface.D I/OIn GPIO mode, this pin is a user-configurable input or output for the StandardComm Interface.D inIn modem control mode, this pin is the Data Set Ready control input (activelow) for the Standard Comm Interface.Asynchronous data output (UART Transmit) for the Standard Comm Interface.RI SCIGPIO.0 SCI24*DCD SCIGPIO.1 SCI23*DTR SCIGPIO.2 SCI22*DSR SCIPower In I/O Supply Voltage Input.Ground. Must be tied to ground.D I/ODevice Reset. Open-drain output of internal POR or VDD monitor. An externalsource can initiate a system reset by driving this pin low for the time specifiedin Table 4.Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.TXD SCI21D OutRXD SCI20D InAsynchronous data input (UART Receive) for the Standard Comm Interface.RTS SCI19*D OutReady to Send control output (active low) for the Standard Comm Interface.*Note: Pins can be left unconnected when not used.Rev. 1.27

CP2105Table 7. CP2105 Pin Definitions (Continued)NamePin #TypeCTS SCI18*D InSUSPEND17*D OutIn GPIO mode, this pin indicates whether the device is in the USB Suspend ornot. The polarity can be configured via the configuration PROM, and defaultsto active-low.D InIn modem control mode, this pin is the Ring Indicator control input (active low)for the Standard Comm Interface.RI ECINC16*—DCD ECID InVPPSpecialGPIO.0 ECI15*DTR ECIGPIO.1 ECI14*DSR ECIDescriptionClear To Send control input (active low) for the Standard Comm Interface.In GPIO mode, this pin is not used.In modem control mode, this pin is the Data Carrier Detect control input(active low) for the Enhanced Comm Interface.Additionally, in either mode programming of the configuration ROM via theUSB interface can be accomplished if a 4.7 F capacitor is connectedbetween this pin and GND.D I/OIn GPIO mode, this pin is a user-configurable input or output for theEnhanced Comm Interface.D OutIn modem control mode, this pin is the Data Terminal Ready control output(active low) for the Enhanced Comm Interface.D I/OIn GPIO mode, this pin is a user-configurable input or output for theEnhanced Comm Interface.D inIn modem control mode, this pin is the Data Set Ready control input (activelow) for the Enhanced Comm Interface.Asynchronous data output (UART Transmit) for the Enhanced Comm Interface.TXD ECI13D OutRXD ECI12D InAsynchronous data input (UART Receive) for the Enhanced Comm Interface.RTS ECI11*D OutReady to Send control output (active low) for the Enhanced Comm Interface.CTS ECI10*D InClear To Send control input (active low) for the Enhanced Comm Interface.*Note: Pins can be left unconnected when not used.8Rev. 1.2

GPIO.0 SCI / DCD SCIGPIO.1 SCI / DTR SCIGPIO.2 SCI / DSR SCITXD SCIRXD SCIRTS SCI242322212019CP2105SUSPEND / RI SCI118CTS SCIGND217SUSPEND / RI ECID 316NC / DCD ECI / VPPD-415GPIO.0 ECI / DTR ECIVIO514GPIO.1 ECI / DSR ECIVDD613TXD ECICP2105-GMTop View1112RTS ECIRXD ECI9RST108VBUSCTS ECI7REGINGND (optional)Figure 2. QFN-24 Pinout Diagram (Top View)Rev. 1.29

CP21054. QFN-24 Package SpecificationsFigure 3. QFN-24 Package DrawingTable 8. QFN-24 Package DD2eEE20.700.000.180.750.020.254.00 BSC.2.700.50 BSC.4.00 150.100.050.08——2.552.552.802.80Notes:1. All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except forcustom features D2, E2, Z, Y, and L, which are toleranced per supplier designation.4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small BodyComponents.10Rev. 1.2

CP2105Figure 4. QFN-24 Recommended PCB Land PatternTable 9. QFN-24 PCB Land Pattern 03.904.004.00X2Y1Y22.700.652.702.800.752.800.50 BSC0.200.30Notes:General1. All dimensions shown are in millimeters (mm) unless otherwise noted.2. This Land Pattern Design is based on the IPC-7351 guidelines.Solder Mask Design3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the soldermask and the metal pad is to be 60 m minimum, all the way around the pad.Stencil Design4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be usedto assure good solder paste release.5. The stencil thickness should be 0.125 mm (5 mils).6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.7. A 2x2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the centerpad.Card Assembly8. A No-Clean, Type-3 solder paste is recommended.9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for SmallBody Components.Rev. 1.211

CP21055. USB Function Controller and TransceiverThe Universal Serial Bus (USB) function controller in the CP2105 is a USB 2.0 compliant full-speed device withintegrated transceiver and on-chip matching and pullup resistors. The USB function controller manages all datatransfers between the USB and the UARTs as well as command requests generated by the USB host controllerand commands for controlling the function of the UARTs and GPIO pins.The USB Suspend and Resume states are supported for power management of both the CP2105 device as well asexternal circuitry. The CP2105 will enter Suspend mode when Suspend signaling is detected on the bus. Onentering Suspend mode, the SUSPEND signals will be asserted if the corresponding interface is configured forGPIO mode. SUSPEND is also asserted after a CP2105 reset until device configuration during USB Enumerationis complete. SUSPEND is active-low by default, but can be configured using the PROM to be active high.The CP2105 exits the Suspend mode when any of the following occur: Resume signaling is detected or generated,a USB Reset signal is detected, or a device reset occurs. On exit of Suspend mode the SUSPEND signal is deasserted. SUSPEND is weakly pulled to VIO in a high impedance state during a CP2105 reset. If this behavior isundesirable, a strong pulldown (10 k ) can be used to ensure SUSPEND remains low during reset.The logic level and output mode (push-pull or open-drain) of various pins during USB Suspend is configurable inthe PROM. See Section 9 for more information.6. Asynchronous Serial Data Bus (UART) InterfacesThe CP2105 contains two UART interfaces, known as the Enhanced Communications Interface (ECI) andStandard Communications Interface (SCI)Each UART interface consists of the TXD (transmit) and RXD (receive) data signals as well as RTS and CTS flowcontrol signals. Optionally, the modem control signals DSR, DTR, DCD, and RI can be enabled for each interface.If modem control signals are not required for the application, these pins can be configured to operate with alternatefunctions, such as GPIO and SUSPEND signals. The UARTs support RTS/CTS, DSR/DTR, and X-On/X-Offhandshaking. The UARTs are programmable to support a variety of data formats and baud rates. The ECI supportsseveral additional UART configuration options beyond those supported by the SCI. If the Virtual COM Port driversare used, the data format and baud rate are set during COM port configuration on the PC. If the USBXpress driversare used, the CP2105 is configured through the USBXpress API. The data formats and baud rates available toeach interface are listed in Table 10.Table 10. Data Formats and Baud RatesInterfaceEnhanced Communication Interface (ECI)Standard Communication Interface (SCI)Data Bits15, 6, 7, and 88Stop Bits1, 1.52, and 21None, Even, Odd, Mark, SpaceNone, Even, Odd300 bps to 2.0 Mbps32400, 4800, 7200, 9600, 14400, 19200, 28800,38400, 56000, 57600, 115200, 128000,230400, 460800, 921600Parity TypeBaud RateNotes:1. Data sizes of 5 and 6 bits are not supported at baud rates above 921600 bps.2. 1.5 stop bits only available when using 5 data bits.3. See “6.1. ECI Baud Rate Generation” for more details on possible baud rates for the ECI interface.12Rev. 1.2

CP21056.1. ECI Baud Rate GenerationThe baud rate generator for the enhanced interface is very flexible, allowing the user to request any baud rate inthe range from 300 bps to 2.0 Mbps. If the baud rate cannot be directly generated from the 48 MHz oscillator, thedevice will choose the closest possible option. The actual baud rate is dictated by Equation 1 and Equation 2.Prescale 4 if Requested Baud Rate 365 bpsPrescale 1 if Requested Baud Rate 365 bps48 MHzClock Divider -------------------------------------------------2 Prescale Requested Baud RateEquation 1. Clock Divider Calculation48 MHzActual Baud Rate --------------------------2 Prescale Clock DividerPrescale 4 if Requested Baud Rate 365 bpsPrescale 1 if Requested Baud Rate 365 bpsEquation 2. Baud Rate CalculationMost baud rates can be generated with an error of less than 1.0%. A general rule of thumb for the majority of UARTapplications is to limit the baud rate error on both the transmitter and the receiver to no more than 2%. The clockdivider value obtained in Equation 1 is rounded to the nearest integer, which may produce an error source. Anothererror source will be the 48 MHz oscillator, which is accurate to 0.25%. Knowing the actual and requested baudrates, the total baud rate error can be found using Equation 3.Actual Baud RateBaud Rate Error (%) 100 1 – --------- 0.25% Requested Baud Rate Equation 3. Baud Rate Error CalculationThe UART also supports the transmission of a line break. It can be set to transmit indefinitely until a stop commandis sent from the application.7. GPIO Mode and Modem ModeEach interface on the CP2105 can be configured in either GPIO Mode or Modem Mode. This allows the SCI andECI to have either modem control signals or GPIO signals available at various pins. Table 11 shows the functionsthat are available in each mode.By default, both interfaces are configured for GPIO Mode.Table 11. CP2105 Modem Mode and GPIO edCommunicationsInterfacePin #Modem ModeGPIO Mode24DCD SCIGPIO 0 SCI23DTR SCIGPIO 1 SCI22DSR SCIGPIO 2 SCI1RI SCISUSPEND SCI15DTR ECIGPIO 0 ECI14DSR ECIGPIO 1 ECI17RI ECISUSPEND ECIOnly one mode can be selected for each interface. Also, the mode of the CP2105 can only be configured once andcannot be reset to the default configuration after being programmed. Refer to “AN223: Runtime GPIO Control forCP210x” for more information on how to configure the port pins of the CP2105.Rev. 1.213

CP21058. GPIO PinsThe CP2105 supports five user-configurable GPIO pins for status and control information. The StandardCommunication Interface (SCI) has three GPIO pins and the Enhanced Communication Interface (ECI) has twoGPIO pins. To use the pins as GPIO pins, the interface with the GPIO pins must be configured in GPIO Mode. Bydefault, both communication interfaces on the CP2105 are configured for GPIO Mode. If the Modem Controlsignals are needed, the interface must be configured for Modem Mode. See Section 7 for more information onModem Mode.Each of these GPIO pins are usable as inputs, open-drain outputs, or push-pull outputs. Four of the GPIO pins alsohave alternate functions listed in Table 12 (GPIO.2 SCI does not have an alternate function).Table 12. GPIO Mode Alternate FunctionsGPIO PinAlternate FunctionGPIO.0 ECITX ToggleGPIO.1 ECIRX Toggle/RS-485 Transceiver ControlGPIO.0 SCITX ToggleGPIO.1 SCIRX ToggleBy default, all of the GPIO pins are configured as a GPIO input. The configuration of the pins is one-timeprogrammable for each device. The difference between an open-drain output and a push-pull output is when theGPIO output is driven to logic high. A logic high, open-drain output pulls the pin to the VIO rail through an internal,pull-up resistor. A logic high, push-pull output directly connects the pin to the VIO voltage. Open-drain outputs aretypically used when interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to thehigher, external voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured asinputs or outputs are not recommended for real-time signalling.More information regarding the configuration and usage of these pins can be found in “AN721: CP21xx DeviceCustomization Guide” and “AN223: Runtime GPIO Control for CP210x” available on the Silicon Labs website.8.1. GPIO.0-1—Transmit and Receive ToggleGPIO.0 and GPIO.1 are configurable as Transmit Toggle and Receive Toggle pins for both the EnhancedCommunication Interface and the Standard Communication Interface. These pins are logic high when a device isnot transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 when data transfer is inprogress. Typically, these pins are connected to two LEDs to indicate data transfer.VIOCP2105GPIO.0 – TX ToggleGPIO.1 – RX ToggleFigure 5. Transmit and Receive Toggle Typical Connection Diagram14Rev. 1.2

CP21058.2. GPIO.1 ECI—RS-485 Transceiver Bus ControlGPIO.1 ECI is configurable as an RS-485 bus transceiver control pin or the Enhanced Communication Interfacewhich is connected to the DE and RE inputs of the transceiver. When configured for RS-485 mode, the pin isasserted during UART data transmission as well as line break transmission and the RX Toggle mode is notavailable. The RS-485 mode of GPIO.1 ECI is active-high by default, and is also configurable for active-low mode.CP2105RS-485TransceiverTXRRXDGPIO.1 ECI – RS485REDEFigure 6. RS-485 Transceiver Typical Connection DiagramRev. 1.215

CP21058.3. Hardware Flow Control (RTS and CTS)To utilize the functionality of the RTS and CTS pins of the CP2105, the device must be configured to use hardwareflow control.RTS, or Ready To Send, is an active-low output from the CP2105 and indicates to the external UART device thatthe CP2105’s UART RX FIFO has not reached the watermark level of 191 bytes on the Enhanced Communicationinterface or 63 bytes on the Standard Communication Interface and is ready to accept more data. When theamount of data in the RX FIFO reaches the watermark, the CP2105 pulls RTS high to indicate to the externalUART device to stop sending data.CTS, or Clear To Send, is an active-low input to the CP2105 and is used by the external UART device to indicate tothe CP2105 when the external UART device’s RX FIFO is getting full. The CP2105 will not send more than twobytes of data once CTS is pulled high.CP2105RS232SystemTXTXRXRXRTSRTSCTSCTSFigure 7. Hardware Flow Control Typical Connection Diagram16Rev. 1.2

CP21059. One-Time Programmable ROMThe CP2105 includes an internal one-time programmable ROM that may be used to customize the USB Vendor ID(VID), Product ID (PID), Product Description String, Power Descriptor, Device Release Number, Interface Strings,and Device Serial Number as desired for OEM applications. If the programmable ROM has not been programmed,the default configuration data shown in Table 13 and Table 14 is used.Table 13. Default USB Configuration DataNameValueVendor ID10C4hProduct IDEA70hPower Descriptor (Attributes)80h (Bus-powered)Power Descriptor (Max. Power) 32h (100 mA)Release Number0100h (Release Version 01.00)Serial StringUnique 8 character ASCII string (16 characters maximum)Product Description String“CP2105 USB to UART Bridge Controller” (47 characters maximum)ECI Interface String“Enhanced COM Port” (32 characters maximum)ECI Operating ModeGPIO modeSCI Interface String“Standard COM Port” (32 characters maximum)SCI Operating ModeGPIO modeTable 14. Default GPIO, UART, and Suspend Configuration DataNameValueGPIO.0 ECI/DTR ECIGPIO InputGPIO.1 ECI/DSR ECIGPIO InputGPIO.0 SCI/DCD SCIGPIO InputGPIO.1 SCI/DTR SCIGPIO InputGPIO.2 SCI/DSR SCIGPIO InputFlush BuffersFlush ECI and SCI TX and RX FIFO on openSUSPEND/RI ECIPush-pull, Active-LowSUSPEND/RI SCIPush-pull, Active-LowRS-485 LevelActive-HighWhile customization of the USB configuration data is optional, customizing the VID/PID combination is stronglyrecommended. A unique VID/PID combination will prevent the driver from conflicting with any other USB driverfrom a different manufacturer’s product. A vendor ID can be obtained from www.usb.org or Silicon Labs canprovide a free PID for the OEM product that can be used with the Silicon Labs VID. Device serialization is done atthe factory to guarantee the ability to uniquely identify a specific device on the USB bus and other applications.This is accomplished by setting the serial number descriptor string that may be queried by the host. By default, aunique 32-bit serial number will be generated for each device at the factory. This number will be converted to aneight-character hexadecimal string. Custom serialization can also be requested.The configuration data ROM can be programmed by Silicon Labs prior to shipment with the desired configurationinformation. It can also be programmed in-system over the USB interface by adding a capacitor to the PCB. If theconfiguration ROM is to be programmed in-system, a 4.7 µF capacitor must be added between the NC/DCD ECI/VPP pin and ground. No other circuitry should be connected to NC/DCD ECI/VPP during a programmingoperation, and VDD must remain at 3.3 V or higher to successfully write to the configuration ROM.Rev. 1.217

CP210510. Voltage RegulatorThe CP2105 includes an on-chip 5 to 3.45 V voltage regulator. This allows the CP2105 to be configured as either aUSB bus-powered device or a USB self-powered device. A typical connection diagram of the device in a buspowered application using the regulator is shown in Figure 8. When enabled, the voltage regulator output appearson the VDD pin and can be used to power external devices. See Table 5 for the voltage regulator electricalcharacteristics.If it is desired to use the regulator to provide VDD in a self-powered application, the same connections fromFigure 8 can be used, but connect REGIN to an on-board 5 V supply, and disconnect it from the VBUS pin. Inaddition, if REGIN may be unpowered while VBUS is 5 V, a resistor divider shown in Note 5 of Figure 9 is requiredto meet the absolute maximum voltage on VBUS specification in Table 1.VIONote 24.7 kNote 3CP2105RSTSUSPEND / RI ECI3.45 V Power1-5 FVIOVDDNote 4NC / DCD ECI / VPPGPIO0 ECI / DTR ECI0.1 FGPIO.1 ECI / DSR ECIRTS ECIREGINCTS ECIEnhancedUARTand GPIOSignalsRXD ECI1 FTXD ECIGNDRXD SCIUSBConnectorTXD SCIRTS SCIVBUSVBUSD D D-D-CTS SCISUSPEND / RI SCIGPIO.0 SCI / DCD SCIGNDStandardUARTand GPIOSignalsGPIO.1 SCI / DTR SCIGPIO.2 SCI / DSR SCINote 1Note 1 : Avalanche transient volta

VDD 3.0 to 3.6V, -40 to 85 C unless otherwise specified. Parameter Test Condition Min Typ Max Unit Digital Supply Voltage (VDD) 3.0 — 3.6 V Digital Port I/O Supply Voltage (VIO)1.8—VDD V Voltage on VPP with respect to GND during a ROM programming operation VIO 3.3V 5.75 — VIO 3.6 V Capacitor on VPP for ROM programming — 4.7 — µF