Transcription

Advanced RISC Computing SpecificationVersion 1.2

1991, 1992 MIPS Technology Inc.—Printed in the United States of America.2071 North Shoreline Blvd., Mountain View, California 94039-7311 U.S.A.All rights reserved. This product and related documentation is protected by copyright anddistributed under licenses restricting its use, copying, distribution, and decompilation.No part of this product or related documentation may be reproduced in any form by anymeans without prior written authorization of MIPS and its licensors, if any.RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the United Statesgovernment is subject to restrictions as set forth in DFARS 252.227-7013 (c)(1)(ii) andFAR 52.227-19.THE COPYRIGHT HOLDER DISCLAIMS ALL WARRANTIES OFMERCHANTABILITY AND FITNESS FOR USE, AND FURTHER DISCLAIMS ANYAND ALL DAMAGES ARISING FROM USE OF THIS SPECIFICATIONINCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT, CONSEQUENTIALAND SPECIAL DAMAGES WHICH MAY ARISE FROM ANY USE OF THISSPECIFICATION. THE USER OF THIS SPECIFICATION HEREBY AGREES TOHOLD THE COPYRIGHT HOLDER, ITS AGENTS, PREDECESSORS, ASSIGNS,AND SUCCESSORS HARMLESS FROM ANY DAMAGES, HOWEVERDENOMINATED, WHICH MAY ARISE FROM ITS USE OF THIS SPECIFICATION.THE TECHNICAL MATERIALS IN THIS SPECIFICATION MAY BE COVERED BYONE OR MORE PATENTS. ACCESS TO THIS SPECIFICATION DOES NOTDIRECTLY, INDIRECTLY, OR BY IMPLICATION LICENSE ANY PATENTSWHICH COVER THE MATERIALS SET FORTH HEREIN. POSSESSION OF THISSPECIFICATION DOES NOT AUTHORIZE USE OF THIS SPECIFICATION.THIS SPECIFICATION IS SUBJECT TO CHANGE WITHOUT NOTICE. NOREPRESENTATIONS, EXPRESS OR IMPLIED, BY IMPLICATION, ESTOPPEL OROTHERWISE RESTRICT THE RIGHT TO CHANGE OR REVISE THISSPECIFICATION.USER’S USE OF ANY PORTION OF THIS SPECIFICATION SHALL BE DEEMEDTO BE AN ACCEPTANCE OF THE ABOVE DISCLAIMERS AND CONDITIONSOF USE.TRADEMARKSAll other product names mentioned herein are the trademarks of their respective owners.2

Table of ContentsPreface .111. Introduction to the ARC Specification .141.11.21.31.41.5Covered By the ARC Specification .15Covered By Addenda To The ARC Specification.16Not Specified by the ARC Specification .16Conventions Used In the ARC Specification.16Conformance .17Part 1: Base Specification2. System Architecture .192.1 Architectural Working Statement .192.2 System States.202.2.1 State Diagram.202.3 Software Subsystems .222.3.1 Application Software.232.3.2 Operating System Software .232.3.3 Hardware Abstraction Layer (HAL) Software .232.3.4 Device Drivers .242.3.5 Loader, Installer, and Independent Utility Software.242.4 Hardware Subsystems.252.4.1 Processing Subsystems.252.4.2 Peripheral Attachment Subsystems .252.5 Firmware .262.6 System Interface Definitions .263

Contents3. Platform Hardware .273.1 System Configurations.273.2 Server System Configuration.28Consequences of Non-Compliance.293.2.1 Processor Unit .303.2.2 Floating Point Unit .313.2.3 Cache.313.2.4 Memory .313.2.5 Timing Function Support .313.2.6 Real Time Clock.323.2.7 System Timer .323.2.8 Console.323.2.9 CD-ROM.323.3 Desktop System Configuration.323.3.1 Keyboard .32Requirements.333.3.2 Pointing Device .33Requirements.333.3.3 Video Subsystem.34Requirements.343.3.4 Audio.353.4 Optional Hardware .373.4.1 Floppy Drive .373.4.2 Serial Ports .373.4.3 Parallel Port.383.4.4 SCSI Interface .393.4.5 Network Interface.40Ethernet .40Token Ring.403.5 Additional Hardware .413.6 Media Formats.413.6.1 Media Formats for System Load .423.6.2 System Partition Formats .423.6.3 Diskettes (5 1/4-inch and 3 1/2 inch) .423.6.4 CD-ROM.433.6.5 Disk Storage Devices .433.6.6 Network.433.6.7 Data Interchange .443.7 Processing Subsystem.443.7.1 Related Consequences.453.8 Peripheral Attachment Subsystems (I/O Bus) .463.8.1 Requirements.463.8.2 Related Consequences.464

Contents4. Platform Firmware.474.1 Firmware Conventions.474.1.1 Calling Procedures .47Parameter Passing.48Status Codes .484.1.2 Memory Utilization .494.1.3 Stack and Data Addressability.504.1.4 Object Formats .504.2 The Firmware Environment.514.2.1 Exception Block .514.2.2 System Parameter Block.514.2.3 Restart Block.53Restart Procedure .544.2.4 Environment Variables.55Console Initialization Environment Variables.55Software Loading Environment Variables.56Time Zone Environment Variable .57Firmware Search Path Environment Variable .574.2.5 System Configuration Data .57Component Class and Type.59Component Flags.63Component Version and Revision .64Component Key.64Affinity Mask .65Configuration Data Size .66Component Identifier.66System Topology Constraints.674.2.6 Additional Configuration Data .674.2.7 Devices, Partitions, Files, and Path Specifications.71Path Specifications .724.2.8 System Partition .734.3 Standard Firmware Functions.754.3.1 Program Loading.754.3.2 Program Termination .784.3.3 Configuration Functions.794.3.4 Input/Output Functions.824.3.5 Environment Functions .914.3.6 Miscellaneous Functions .924.3.7 The Firmware Function Vector .964.3.8 Platform-Specific Firmware Functions.974.3.9 Adapter-Specific Firmware Functions.974.4 Loaded-Program Conventions .974.5 Interrupts and Exceptions .100Invoking Exception Handlers .100Exception Handler Routines.101Loaded Program Access to Exceptions .1015

Contents5. System Console .1025.1 Functionality.1025.1.1 Basic Console Input .1025.1.2 UNICODE Console Input .1045.1.3 Basic Console Output.1045.1.4 UNICODE Console Output.1075.2 Operational Characteristics .1086. Multiprocessor Platforms .1096.1 MP Architecture Overview.1096.2 Processor Subsystem and Caches .1106.2.1 Processor Instruction set.1106.2.2 User Application Portability Considerations .1106.2.3 Symmetry and Shared Memory .1106.2.4 Homogeneity of CPUs.1106.2.5 Hardware-Enforced Cache Coherency .1116.2.6 Cache Coherency During I/O Transfers .1116.2.7 Atomic Writes .1116.2.8 Strong Ordering.1116.2.9 Processor Identification.1116.2.10 Timer Interrupts .1126.2.11 Optional Powerfail Interrupt .1126.3 I/O Subsystem .1126.3.1 Symmetry .1126.4 Interprocessor and I/O interrupts.1126.4.1 Interprocessor Interrupts .1126.4.2 Interprocessor Interrupt Priority.1136.4.3 I/O interrupt Assignment .1136.5 Boot and Reset functions.1136.5.1 Boot Master CPU .1136.5.2 Starting CPUs.1136.5.3 Program Termination Function Semantics for MP Machines.114Part 2: Developing Material7. Network Bootstrap Protocol Mappings.1167.1 BOOTP/TFTP/UDP/IP/ARP Protocols.1167.2 Networked System Partition .1177.2.1 BOOTP/TFTP Protocol References.1177.2.2 System Interface Mapping.118Open() .118Read().119Write() .119Close() .119GetReadStatus().1196

ContentsMount() .120Seek() .120GetDirectoryEntry() .1207.2.3 Protocol Clarifications.121Token-Ring MAC Requirements.121Ethernet MAC Requirements .121LLC Requirements .121BOOTP Request Frame Requirements.122BOOTP Response Frame Requirements .122TFTP RRQ Frame Requirements .122TFTP ERROR Frame Requirements .123ICMP Frame Requirements .123ARP Frame Requirements .1237.2.4 Server Considerations .124BOOTP vs. RARP.124LLC Support.124Filename Support .1247.3 IBM DLC RIPL/LLC Protocols .1247.3.1 Protocol References .1257.3.2 System Interface Mapping.125Open() .125Read().126Write() .126Close() .126GetReadStatus().126Mount() .127Seek() .1277.3.3 Protocol Clarifications.127Token-Ring MAC Requirements.128Ethernet MAC Requirements .128FIND Frame Requirements .128FOUND Frame Requirements .130SEND.FILE.REQUEST Frame Requirements .130FILE.DATA.RESPONSE Frame Requirements.132LOAD.ERROR Frame Requirements.132PROGRAM.ALERT Frame Requirements .1327.3.4 Server Considerations .133Glossary .1347

FiguresFigure 2-1System States.20Figure 2-2Firmware State.21Figure 2-3Program State .22Figure 3-16 Position DIN connector for EISA Keyboard/Mouse Connectors .34Figure 3-215-Pin D SUB for EISA Video Connector .34Figure 3-3Combination Receptacle for EISA Video Connector .34Figure 3-49-Pin D-SUB for Asynchronous Serial.38Figure 3-525-Pin D-SUB for Parallel Connector .39Figure 3-650-Pin Single Ended SCSI Connector .39Figure 3-7Ethernet BNC Jack .40Figure 3-8RJ-45 Connector.40Figure 3-915-Pin D-SUB receptacle for Ethernet AUI Connector.40Figure 3-109-Pin D-Sub plug connector for Token Ring.41Figure 4-1System Parameter Block Structure .51Figure 4-2RestartBlock .53Figure 4-3Boot Status Bits .54Figure 4-4Example System .58Figure 4-5COMPONENT Data Structure .598

TablesTable 3-1Keyboard Standard .33Table 3-2Pointing Device Characteristics.33Table 3-3Video Characteristics.34Table 3-4ARC System Audio Requirements.36Table 3-5Audio Interface Electrical Requirements.36Table 3-6Recommended Audio Connectors .36Table 3-7Serial Interface Characteristics .38Table 3-8Parallel Interface Characteristics .38Table 3-9SCSI Interface Characteristics.39Table 3-10Possible Ethernet Media Connectors .40Table 4-1Status Codes .48Table 4-2Component Flag Bit Usage.64Table 4-3Path Mnemonics .72Table 4-4Firmware Vector.96Table 5-1Function Key Control Sequences .103Table 5-2Control Sequences .105Table 5-3Additional SGR Control Sequences .106Table 5-4Single Character Control Functions.1079

Code SamplesCode Example 4-1Exception Handling .100Code Example 4-2Restoring Registers .10110

PrefaceThe Advanced RISC Computing Specification has been developed to define a set ofstandard capabilities for MIPS based computing systems. These capabilities have beenchosen to allow significant opportunities for innovation by platform developers while atthe same time presenting a standard environment for operating system and applicationsoftware.The goal of all participants has been to promote the development of a new class ofcomputing systems. They provide for the vendor innovation that is usually characteristicof only proprietary systems, along with the ubiquity of systems typically based on rigidhardware standards such as the PC.This specification was developed as a group effort by members of the AdvancedComputing Environment (ACE) initiative. Early in the process of the development of thisspecification, representatives from several companies worked closely together to write theoriginal drafts of the specification.The companies involved in writing the original draft of this specification were CompaqComputer Corporation, Silicon Graphics Computer Systems, The Santa Cruz Operation,MIPS Computer Systems Inc., Digital Equipment Corporation, and MicrosoftCorporation. The initial drafts of this specification were distributed to all members of theACE initiative for review, and the feedback from many reviewers was incorporated.11

PrefaceHow This Book Is OrganizedThis book is organized in the following fashion:Chapter 1, “Introduction to the ARC Specification,” is an overview of thespecification itself, describing what it does and does not cover.Chapter 2, “System Architecture,” describes the software, hardware, and firmwarelayers.Chapter 3, “Platform Hardware,” defines what standard and optional hardware makeup a system, the technical specifications for these items, and specific configurationsdefined by the specification.Chapter 4, “Platform Firmware,” describes the conventions, environment, andfunctions performed by the firmware.Chapter 5, “System Console,” describes the feature set of the console.Chapter 6, “Multiprocessor Platforms,” describes hardware and firmware changes tosupport multiprocessors.Chapter 7, “Network Bootstrap Protocol Mappings,” describes the mapping ofnetwork protocols onto ARC I/O functions.Glossary is a list of words and phrases found in this book and their definitions.Cited ReferencesThe following documents are referenced in the ARC Specification: ANSI X3.64 - 1979. Additional Control for Use with American National StandardCode for Information Interchange. Issuing Organization ANSI - American NationalStandards Institute. ANSI X3.131-1990 (Revision 10c). Information Systems - Small Computer SystemInterface (SCSI) Document Number: X3.131, Issuing Organization ANSI American National Standards Institute. EIA 232 - 1990. Electrical Industries Association. IEEE 802.4-90. Information Processing Systems - Local Area Networks - Part 4:Token-Passing Bus Access Method and Physical Layer Specifications First Edition(IEEE Computer Society Document).IEEE 802.3-90. Information Processing Systems - Local Area Networks - Part 3:Carrier Sense Mult. Access with Collision Detection (CSMA/CD) Access Method andPhys. Layer Spec (IEEE Computer Society Doc.) Second Edition (ISO 8802 .3 1990).Correction Sheet - 1990, Supp. 802.3H - 1990, Supp. 802.3I - 1990.12

Preface IEEE 802.5-89. Standards for Local Area Networks Token Ring Access Method andPhysical Lay

specification. the user of this specification hereby agrees to hold the copyright holder, its agents, predecessors, assigns, and successors harmless from any damages, however denominated, which may arise from its use of this specification. the technical materials in this specification may be covered by one or more patents.