Contents 3SPERRY UNIVAC 05/3ASSEMBLERUP-8913PART 2. STORAGE AND SYMBOL DEFINITIONS5.e6.STORAGE .5.1.7.STORAGE USAGEDefine ConstantDefine StorageDuplication FactorDefinition TypeLength FactorConstant .DEFINITION TYPESCharacter ConstantsHexadecimal ConstantsBinary ConstantsPacked Decimal ConstantsZoned Decimal ConstantsHalf-Word Fixed-Point ConstantsFull-Word Fixed-Point ConstantsHalf-Word Address ConstantsFull-Word Address ConstantsBase and Displacement ConstantsExternal Address ConstantsFloating-Point )(F)(Y)(A)(S)(V)(E and 5-125-125-135-135-155-155-18SYMBOL DEFINITIONS6.1.EQUIVALENT SYMBOLS6-26.2.SYMBOL APPLICATIONS6-3PART 3. BAL APPLICATION INSTRUCTIONS7.INTRODUCTION TO APPLICATION INSTRUCTIONS7.1.INSTRUCTION AND FORMAT CONVENTIONS7-17.2.EXPLICIT FORMS7-67.3.IMPLICIT FORMS7-67.4.DEFINITIONS OF FORMAT TERMS7-6

,.UP-8913SPERRY UNIVAC OS/3ASSEMBLERContents 48. BRANCHING INSTRUCTIONS8.1.USE OF BRANCHING INSTRUCTIONS8-18.2.EXTENDED MNEMONIC CODES8- AND LINKUse of the BALA Instruction in Base Register Assignment(BAL, BALA)8-58-78.4.BRANCH ON CONDITION(BC, BCR)8-98.5.BRANCH ON COUNT(BCT, BCTR)8-138.6.BRANCH ON INDEX HIGH(BXH)8-158.7.BRANCH ON INDEX LOW OR EQUAL(BXLE)8-188.8.EXECUTE(EX)8-209. DECIMAL AND LOGICAL INSTRUCTIONS9.1.USING DECIMAL INSTRUCTIONS9- PACKED AND UNPACKED CONSTANTSAND MAIN STORAGE AREASPacked Decimal Constants and Main Storage AreasUnpacked Decimal Constants and Main Storage Areas9-39-49-69.3.ADD DECIMAL(AP)9-89.4.COMPARE DECIMAL(CP)9-109.5.DIVIDE DECIMAL(DP)9- Edit PatternThe Resulting Condition CodeExamples of General UsageSummary(ED)9-169-179-239-249-269.7.EDIT AND STORAGE AND SKIPWhat the Instruction Can DoWhat Operands You SupplyHow You Specify Your OperandsSpecifying Basic OperandsSpecifying Destination Data OperandsSpecifying Register Modification OperandsSpecifying Repeat OperandsFormat SummaryMSS Operation ConditionsOperational 9-419-439-449-589-609-60

Contents 11SPERRY UNIVAC OS/3ASSEMBLERUP-891314. LIST ListFIFO ListDouble-ended ListRing with StationPriority ListAged Priority ListTwo-Level List14. IS NEEDED FOR LIST PROCESSING?14.3.LIST CONTROL BLOCK14. PROCESSING LIZING AND USING SYSTEM 80 14-18What System 80 ProvidesWhat You Must Provide14-18ENQUEUEDEQUEUESTEP QUEUESpecifying ElementsSpecifying Lists by TypeLIFO List UsageFIFO List UsageDouble-ended List UsageFIFO with Station UsageRing with Station UsagePriority List UsageAged Priority List Usage14. ELEMENT LISTFEL InitializationFEL Usage14. PROCESSING OPTIONSRegister Load/Store OptionData Movement CONTROL PROGRAMLCP FormatLCP InstructionsNO-OP LCP InstructionMASKED TEST LCP InstructionLOGICAL COMPARE LCP InstructionMASK AND COMPARE LCP InstructionLOAD REGISTERS LCP InstructionSTORE REGISTERS LCP InstructionMOVE DATA OUT LCP InstructionMOVE DATA IN LCP InstructionSTEP STATION LCP InstructionINIT STATION LCP InstructionSWITCH LIST SCAN LCP InstructionInitializing and Calling List Control 4-5114-5214-5314-5514-5614-5714-5814-5914-6114-62


SPERRY UNIVAC OS/3ASSEMBLERUP-8913Contents 17G-1G.2.&SYS TEG.7.&SYS PARMG-2G-2G-3G-4G-5USER COMMENT -9.Writing and Submitting a ProgramCard ImageAssembler Coding FormCoding Form and Card Image RelationshipExample of Proper Coding TechniquesCOBOL Source CodeObject Code Generated from COBOL Source Code1-11.Assembly ListingOS/3 Object Module FormatOS/3 Load Module FormatAssemble, Link, and Go Operation2-1.2-2.Determining Binary ValuesFixed-Point Number Formats4-1.4-2.Assembler Format RelationshipsByte and Word Structure5-1.Floating-Point Number Formats7-1.Instruction Formats8-1.Program Status Word Diagram9-1.9-2.9-3.9-5.9-6.9-7.9-8.Basic MSS ExecutionMSS Execution with Destination FeatureMSS Execution with Register Modification FeatureMSS Execution with Repeat FeatureOperand 2 FormatDestination Operand FieldsRepeat FieldsFormat Fields10-1.Comparison of Binary Numbers and Values Expressed in Powers of 59-4610-6

UP-8913SPERRY UNIVAC OS/3ASSEMBLER14-1. LIFO List14-2. Adding and Removing Elements from a LIFO List14-3. The Two Types of FIFO Lists14-4. Adding and Removing Elements in FIFO Lists14-5. FIFO List with Station14-6. Ring List with Station14-7. Adding and Removing Elements from a Ring List14-8. Priority List14-9. Adding to a Priority List14-10. Level Stations14-11. Initialized Aged Priority List14-12. Aged Priority List after Table 14-1 Operations14-13. Two-Level List14-14. LCB Format14-15. Specifying an Element in an LCB14-16. Initializing LIFO LCB14-17. Initializing FIFO LCB14-18. Initializing LCB for FIFO with Station14-19. Ring List Initialization14-20. Priority List Initialization14-21. Aged Priority List Initialization14-22. Enqueueing and Dequeueing with FEL14-23. Register Load/Store Option14-24. LCB Fields for Data Movement Option14-25. Registers for Data Movement14-26. LCP Instruction Format14-27. NO-OP Format14-28. MASKED TEST Format14-29. LOGICAL COMPARE Format14-30. MASK AND COMPARE Format14-31. LOAD REGISTERS Format14-32. STORE REGISTERS Format14-33. MOVE DATA OUT Format14-34. MOVE DATA IN Format14-35. STEP STATION Format14-36. INIT STATION Format14-37. SWLS Format22-1.Example of lnline Macro Expansion23-1.23-2.Accessing a Macro Definition Submitted in the Source DeckAccessing a Macro Definition Stored in a Library24-1.24-2.24-3.PROC and MACRO HeadingPROC. MACRO, and Call Instruction ComparisonCommunication between Macroinstruction and Macro DefinitionExample of MACRO and PROC Definitions24-4.Contents 24-824-12TABLES2-1.2-2.Comparison of Numeric ExpressionsHexadecimal Notation4-1.4-2.Comparison of TermsSummary of Operators2-22-44-94-14

SPERRY UNIVAC OS/3ASSEMBLERUP-8913eContents 195-1.5-2.Characteristics of Constant and Storage Definition TypesZero Duplication Area Examples5-25-68-1.8-2.8-3.Extended Mnemonics and FunctionsOperand 1 Mask CombinationsBranch-on-Condition Instruction by Usage8-38-108-119-1.9-2.9-3.9-4.9-5.9-6.9-7.Edit Instruction OperationMSS OperationsFormat Code Values for Operand TypesOp Type ValuesFormat Code Values for Register ModificationMX ValuesMSS Operations and Conditions9-269-329-409-409-429-439-5812-1.Shift Logical Mask 4-9.Operations with Aged Priority ListList Type ValuesPermissible Element/List Type CombinationsList Head Type ValuesStations Used by LCP InstructionsCT Match/Mismatch TableProgram Control Under LCP FieldsINIT STATION Effects on StationsInitializing LCB Registers for LCP 4-6215-1.Assembler Directives15-117-1.Assembler Control Directives17-120-1.Listing Control Directives20-127-1.27-2.27-3.27-4.Conditional Assembly Language StatementsOperator PriorityValid Attribute Reference ApplicationsType Attributes of IT Listing ContentExternal Symbol Dictionary (ESD) Listing ContentCross-Reference ContentDiagnostic Listing Content28-228-328-428-5B-1.B-2.B-3.ASCII (American Standard Code for Information Interchange) Character CodesEBCDIC (Extended Binary Coded Decimal Interchange Code) Character CodesPunched Card, ASCII, and EBCDIC CodesB-1B-2B-3C-1.C-2.Hexadecimal-Decimal Integer ConversionHexadecimal FractionsC-3C-7E-1.E-2.E-3.Mnemonic List of InstructionsAlphabetic Listing of InstructionsList of Instructions by Machine CodeE-1E-5E-11

9-29SPERRY UNIVAC OS/3ASSEMBLERUP-8913Register 1 after execution of EDMK instruction:0000 10000 000010000 000010000 101111011OIOIOOIO0BIbinaryBhexaddress of 1st significant digitRegister 1 after execution of S instruction:0000 I0000 0000 10000 0000 10000 1011 11010O 10IOOIO0BIbinaryAhexaddress of byte to the left of1st significant digitEdited result after execution of MVI instruction:1stsignificantdigit 0100}000 0101-: 1010 1111!0010 011oi1011 1111:0100 1111 lo101 1111 :0111 0100 :1011 1111 :0001 1111-Joooo4II05IlBF Il261· BlF I 4IFI 5jF I 7jI B4lIFj1F I 0lIn this example, the edit mask is moved into a 10-byte field labeled PATTERN.The address of the position where the insert character is to be placed (in theabsence of significant digits before the significance starter) is loaded into register1. Then DATA, containing the packed number, is edited and the result is placedin PATTERN. The address of the first significant byte (in this example, 2 issignificant) replaces the content of register 1. Then a full word containing thedecimal value 1 is subtracted from the content of register 1, therefore movingone byte to the left. The MVI instruction moves the dollar sign into the byteaddressed by the content of register 1.binaryhex

UP-8913SPERRY UNIVAC OS/3ASSEMBLER9-30MSS9.8.MODIFY STORAGE AND SKIP le Program ExceptionsOBJECTINST.LGTH.(BYTES)6Condition Codes SET TO 0 SET TO 1 SET TO 2 SET TO 30UNCHANGED ADDRESSINGDSIGNIFICANCEDDDATA (INVALID SIGN/DIGIT) SPECIFICATION:DECIMAL DIVIDE0NOT A FLOATING-POINT REGISTER0DECIMAL OVERFLOW0OP 1 NOT ON HALF-WORD BOUNDARYDEXECUTE0OP 2 NOT ON HALF-WORD BOUNDARY0EXPONENT OVERFLOW00DDDEXPONENT UNDERFLOW OPERATION PROTECTIONFIXED-POINT DIVIDEOP 2 NOT ON FULL-WORD BOUNDARY. OP 2 NOT ON DOUBLE-WORDBOUNDARYFIXED-POINT OVERFLOW0OP 1 NOT EVEN NUMBERED REGISTERFLOATING-POINT DIVIDE0OP 1 NOT ODD NUMBERED REGISTER SEE OPERATIONAL CONSIDERATIONS0NONEThe modify storage and skip (MSS) instruction performs an operation that you specifyby immediate operand 1 (i,) on two operands indirectly specified by main storageoperand 2. Depending on the result, program control may then pass to the nextsequential instruction or to another location, called the skip location, which is offsetfrom the instruction following the MSS instruction by a displacement value youspecify in immediate operand 3 (i 3 ). You can put the result of the operation in themain storage location or register specified by operand 1.Explicit Format:LABEL[symbol]fl OPERATION flOPERANDMSSImplicit Format:LABEL[symbol]fl OPERATION b.OPERANDMSSThe i 1 and i 3 fields shown in the previous two formats roughly correspond to the 11 and 13fields of other SS-type instructions. The i 1 value is assembled, unchanged in value, into bits8-11 of the MSS object instruction and the i3 value is assembled, likewise unchanged invalue, into bits 12-15. The rest of the operand fields are assembled according to the rulesfor SS-type instructions.

9-31SPERRY UNIVAC OS/3ASSEMBLERUP-89139.8.1.What the Instruction Can DoThe MSS instruction can:1.perform an arithmetic, data movement, or logical operation onoperands, either of which can be in main storage or a register;2.depending on the operation result, branch either to the next sequential instructionor go to the skip location as determined by the i 3 operand;3.optionally store the operation result to a destination operand, either in mainstorage or a register, specified by operand 1;4.optionally modifyperformed; and5.repeat steps 1 through 4.up to twoadditionaltwo sourceregisters each time the operation isAt its simplest, the MSS instruction proceeds as shown in Figure 9-1.EXECUTE MSSSOURCEOPERANDGO TO igure 9-1.YESGO TO SKIPLOCATIONBasic MSS ExecutionAs Figure 9-1 shows, the MSS instruction fetches two operands and performs anoperation on them that you specify by operand i 1 The operations available to you with MSSare shown in Table 9-2. Each operation tests for a condition. If that condition is not met,program control passes to the next sequential instruction after MSS. If the condition is met,however, program control skips forward a number of half words beyond the next sequentialinstruction, to the skip location, and continues with the instruction found there. The numberof half words skipped is given by the absolute value i3 and it can range from 0 to 15 halfwords (30 bytes).

UP-8913SPERRY UNIVAC OS/3ASSEMBLERTable 9-2.9-32MSS Operationsii ValueMnemonic0ADDZAdd and compare for zero res u It1ADDNZAdd and compare for nonzero result2SUBZSubtract and compare for zero result3SUBNZSubtract and compare for nonzero result4MCEMove and compare for equal result5MCNEMove and compare for unequal result6MCLEMove and compare for less than or equal result7MCHMove and compare for greater than result8ANDZAND operands and test for zero result9ANDNZAND operands and test for nonzero resultAXORZXOR operands and test for zero resu ItBXOR NZXOR operands and test for nonzero resultcORZOR operands and test for zero resultDORNZOR operands and test for nonzero resultDescriptionAs you can see, each of the operations in Table 9-2 tests its result for a certaincondition. Program flow depends on whether the result does or does not satisfy thatcondition. If the condition is satisfied, the i3 displacement is added to the currentprogram status word {PSW), in effect causing a branch to the resulting location. If thecondition is not met, program control passes to the next sequential instruction. Whatthe conditions are and how they are met is described in 9.8.4.Besides the basic functions described so far, you can optionally put the operationresult in a destination operand as shown in Figure 9-2.

9-33SPERRY UNIVAC OS/3ASSEMBLERUP-8913EXECUTE MSSSOURCEOPERAND GO TO igure 9-2.YESGO TO SKIPLOCATIONMSS Execution with Destination FeatureThe destination operand of Figure 9-2 can be a register or a location in mainstorage. In addition to this feature, you can modify one or two additional registers(Figure 9-3):



UP-8913SPERRY UNIVAC OS/3ASSEMBLER9-36If the operation condition is satisfied, the instruction skips to the main storagelocation specified by i 3 . If the condition is not satisfied, the instruction will decrementthe repeat count (whose initial value you supply) by 1. If after this the count remainsnonzero, control returns to the MSS operation and the process is repeated using theupdated data in the operands. If the count reaches zero, control passes to the nextsequential instruction. If during a repetition, the operation condition is satisfied,regardless of the repeat count value, program control passes to the skip locationspecified by i 3 .You can code an MSS instruction using any combination of the features described inFigures 9-2 through 9- Operands You SupplyThis section describes the format of the data you use in the MSS instruction. Exactlyhow you specify this data is described in 9.8.3; what you see here is an expansion ofthe MSS operations and capabilities previously described.At a minimum, you need to specify the MSS operation, its two operands, and the skiplocation (Figure 9-1 ). OperationFourteen operations are available as described in Table 9-2. All operations useall the bits in each operand. They are descibed in more detail in 9.8.4. OperandsThe MSS instruction always uses two source operands: one named the primarysource data (PSD), and the other the secondary source data (SSD). They can bothreside in main storage, both in registers, or one in main storage and one in aregister. Both operands are equal in length, and can be one, two, three, or fourbytes long. The operands are aligned as follows:specifiedlocationiM ;o """''I. . . . , .1 byte2 bytes 3 b es .4 b es .-

9-37SPERRY UNIVAC esMultibyte MSS operands in main storage occupy contiguous bytes starting at thespecified location and no half-word or full-word boundary alignment is necessary.In a register, the low order byte of an operand must always be aligned with thelow order eight bits of the register. The two source operands may overlap. Skip LocationSpecified by i 3 , this half byte of data represents the number of half words bywhich program control skips if the operation condition is met. Up to 15 halfwords (30 bytes) can be specified, and all skips must be in a forward direction.If you want to keep the result of your MSS operation (Figure 9-2), you need tospecify a destination data (DD) operand. You do this using the operand 1 address ofyour MSS source instruction. The operand can be stored in main storage, at theoperand 1 address, or it can be put in a register specified by the b 1 field (in whichcase the d 1 value is ignored). The DD length is equal to that of the two sourceoperands and its alignment within main storage or a register follows the same rulesthat they do. It can, in fact, overlap one or both of the source operands.If you want to modify additional registers, you can specify up to two of them. Foreach one, you may also need to specify a register modification value (RMV), a 16-bitinteger that is added to or subtracted from its modified register.If you want to repeat the MSS operation, you need to specify an initial value for therepeat count. The count can reside in main storage, in which case it is 8 bits long,or it can occupy 32 bits in a register.9.8.3.How You Specify Your OperandsTo complement the operands of the MSS source instruction, you use a 4-word areain main storage to specify exactly how you want the instruction to execute. The area,which you must align on a double-word boundary, is addressed by operand 2. Fieldswithin the operand 2 area specify the source operands, if and how the MSS operationis to repeat, if and how registers are to be modified, and so on. The basic format ofoperand 2 is shown in Figure 9-5.

UP-89139-38SPERRY UNIVAC OS/3ASSEMBLERBITWORD 001284OPR S TYPEFORMATCODER1R222016242831PRIMARY SOURCE DATAMODIFYRXMODIFYRYREPEAT COUNTRMV13SECONDARY SOURCE DATAFigure 9-5. Operand 2 Format9.8.3.1.Specifying Basic OperandsTo use the simplest form of the MSS instruction (Figure 9-1) you need to specify thesource operands as follows: Primary Source OperandYou can specify the primary source operand using word 0 in one of three ways:1.2.Within a register, called the primary source data register (PSDR), specified inword 0:Bit,IOWord 0LPSDR,311- -JAt a main storage address given in RX form by the primary source base register(PSBR) and the primary source data displacement (PSDD):Bit -----------------116Word 0 :L- -3.t:J619-- ----- --- --19120311PSBRPSDD- - . .Or, at a main storage location whose 24-bit address is contained in thelogical primary source data address (LPSDA): ------BitWord 0 :L- - - - - - ---18311LPSDA--------------------------

UP-8913 9-39SPERRY UNIVAC OS/3ASSEMBLERSecondary Source OperandYou can specify the secondary source data using word 3 in one of four ways:1.Within a register, called the secondary source data register (SSDR); specifiedin word 3:Bit ---------------- 619Word 3 ::- - - - - - - - - - - - .JAt a main storage address given in RX form by the secondary source base register(SSBR) and the secondary source data displacement (SSDD):BitWord 33.! SSDRL--------- ------ 2.L - - - . .lIJ' s s s B R 1 9.2 o s s oo 3 .1At a main storage location whose 24-bit address is contained in the logicalsecondary source data address (LSSDA):Bit -18311 3: ML------ - -'----------------------- 4.Or, as immediate data, from one to four bytes in length:BitWord 3lo1 II"I1243111 byte2 bytes3 bytes4 bytesNote that byte alignment for PSD immediate data follows the same rules asalignment within a register. Format CodeBecause you can specify the PSD in one of 3 ways and the SSD in one of 4 ways, thisresults in 1 2 possible format combinations. You must, therefore, specify to the MSSinstruction which one of these 12 combinations it is to operate with. You do this withthe format code, bits 4-7 of word 0. Its possible settings are shown in Table 9-3.

UP-8913Table 9-3.Format Code Values for Operand TypesFormat Code (Hex) 9-40SPERRY UNIVAC OS/3ASSEMBLERPSD TypeSSD placementRegisterOperand Type (Op Type)You use this field, located in bits 2 and 3 of word 0, to specify the length of thesource operands with which the MSS instruction is to operate. If you specify adestination operand, this field specifies its length also. Its possible values are aslisted in Table 9-4.Table 9-4.Binary ValueOp Type ValuesOperand Length (bytes)001012103114

UP-8913SPERRY UNIVAC OS/3ASSEMBLER9. Destination Data OperandsTo store the result of an MSS operation, as in Figure 9-2, you need to use thefollowing operands: Store Indicator (S)Located in word 0, bit 1, this 1-bit field lets you specify whether or not theoperation result is to be stored in the destination operand. You put a 1 in thisfield to indicate storage, or a zero to suppress storage. Destination Data Format (DDF)You use this 1-bit field in word 1, bit 18 to indicate whether the operation result is tobe put in a register or in main storage. You specify a zero to indicate result storage inthe main storage location specified by the operand 1 base/displacement address. Youput a 1 in this field to indicate that the result is to go directly in the register specified byb1 in operand 1 (ignoring the d 1 field). Regardless of the setting of this field, no storageoccurs if the store indicator is set to Register Modification OperandsYou can specify one or two additional registers to be modified as in Figure 9-3.Each of these registers, called register X (RX) and register Y (RY), can be specified inthe operand 2 area as a source operand base register or as a separate register. Inoperation these registers are modified once for each execution of the MSS operationthat does not meet the operation's conditions. You can specify the initial values of RXand RY. You can specify the values used to modify these registers with one or tworegister modification value (RMV) fields. Finally, you can use the modify register(MX/MY) fields to specify exactly how modification is to take place. Primary Source Base Register (PSBR)This register, discussed earlier, can be modified using the MODIFY and RMVfields. You can use this feature to modify the effective address of the primarysource field, causing it to address successive areas of main storage for eachexecution of the MSS operation. Base register 0 always has a zero value foraddress computation purposes, but the other 15 registers can be used for addressmodification. Secondary Source Base Register (SSBR)This register can be modified in the same way as the PSBR described earlier. Modification Register 1 (R1)You can specify that a register other than a source base register be modified.You do so by putting the register number in this 4-bit field at word 1, bits 0--3.

9-42SPERRY UNIVAC OS/3ASSEMBLERUP-8913Modification Register 2 (R2)You can specify that a second register other than a source base register bemodified. You do so by putting the register number in this 4-bit field at word 1,bits 4-7. Register Modification Value 1 (RMV1)You can modify RX or RY by adding or subtracting this 16-bit field contained inword 2, bits 0-15. Register Modification Value 2 (RMV2)In addition to RMV1, you can specify a second 16-bit field to be added to orsubtracted from RX or RY. This field is contained in word 2, bits 16-31. Format CodeIn addition to specifying source data formats, the format code specifies which tworegisters are to be modified, according to Table 9-5.Table 9-5.Format Code Values for Register ModificationFormat CodeRegister XRegister SSBR9PSBRR2APSBRR2BPSBRR2

UP-8913 SPERRY UNIVAC OS/3ASSEMBLER9-43Modify Register X (MODIFY RX)This 4-bit field in word 1, bits 8-11, permits you to specify exactly how registerX is to be modified, according to Table 9-6.Table 9-6.MX Value MX ValuesRegister Modification0No modification1Increment RX by 12Decrement RX by 13Add RMV1 value to RX4Subtract RMV1 value from RX5Add RMV2 value to RX6Subtract RMV2 value from RX7-FNot usedModify Register Y (MODIFY RY)You use this 4-bit field at word 1, bits 12-15, to specify exactly how RY is tobe modified. Register Y modifications and their values are the same as theMODIFY RX values given in Table 9-6.Note that you can modify one register alone if you want: simply enter 0 for theMODIFY field of the other register. Entering 0 in both MODIFY fields preventsany register modification from taking place. Repeat OperandsTo repeat your MSS operation (Figure 9-4), you must specify the following fields: Repeat Indicator (R)This 1-bit field in word 0, bit 0 of the operand 2 area indicates whether or notthe MSS instruction is to repeat its specified operation. Coding a 0 in this fieldcauses the MSS operation to execute exactly once, then terminate. Coding a 1causes the MSS operation to be repeated according to the repeat count.

UP-8913 9-44SPERRY UNIVAC OS/3ASSEMBLERRepeat CountThis field holds a positive binary number that is decremented by 1 after eachrepetition of the MSS operation that does not satisfy the operation condition. If thisquantity reaches zero, the MSS instruction terminates and thereby passes control tothe next sequential instruction. A repeat count of 0 causes a single execution of theMSS operation. A repeat count of n causes n 1 executions as long as no executionsatisfies the operation condition. You can specify the count one of two ways: either asan 8-bit field within the operand 2 area; -BitWord 1- -- - - --- -- -- - - -- - - - - - - -- - - - 2 431-1Irepeat countIIL-------- - -- --- - ----- - ------ --'-----------"or, as a 32-bit register specified by a 4-bit field within the operand 2 area:Bit102831r--------------------------------- repeat1ooumWord 1 1register1L-- ------ --- --- --- -------- --- - -L------'If the repeat count is the 8-bit quantity contained in word 1 (bits 24-31 of operand 2)that value will not change during MSS execution. If, however, the repeat count iscontained in a general register, it will be decremented by 1 for each repetition aspreviously described. Repeat Count Register Indicator (RR)You use this 1-bit field at word 1, bit 19 to indicate whether the repeat count iscontained in the operand 2 area at word 1, bits 24-31 (RR O) or in the generalregister specified in word 1, bits 28-31 (RR 1 ). SummaryTo help you select the one you want to use, all operand 2 formats and their fieldsare summarized in the following three illustrations. Figures 9-6 and 9-7 show theformats for the destination operand and repeat features, respectively; these can beused in all other formats. Figure 9-8 shows the 12 format codes and summarizesthe fields unique to each: Primary Source Data (PSD) Secondary Source Data (SSD) Modification Fields (MODIFY)

9-45SPERRY UNIVAC OS/3ASSEMBLERUP-8913BITWORD 00lsJT E4JSj12p61201241283112412831l l23Figure 9-6.Destination Operand FieldsBITWORD 0014is112116RII J23Figure 9-7.Rep