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Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)1Hardness Assurance for Total Dose and DoseRate Testing of a State-Of-The-Art Off-Shore32 nm CMOS ProcessorKenneth A. LaBel, Robert A. Gigliuto, Carl M. Szabo, Jr., Martin A. Carts, Matthew Kay,Timothy Sinclair, Matthew Gadlage, Adam Duncan, and Dave Ingalls Abstract— Hardness assurance test results of an AdvancedMicro Devices, Inc. (AMD) 32 nm processor for total dose anddose rate response are presented. Testing was performed usingcommercial motherboards and software stress applicationsversus more traditional automated test equipment (ATE).Index Terms— radiation, total dose, silicon on insulator (SOI),processor, test methodI. INTRODUCTIONThere has been much discussion throughout the governmentand industry regarding the International Traffic in Arms(ITAR) regulations as they pertain to radiation-induced devicetolerance [1]. This is a dual-edged sword: How to protect critical U.S. technologies fromunfriendly hands, while at the same time, Commercial semiconductor manufacturers fearinadvertently exceeding the ITAR radiation levels.By utilizing a representative non-U.S. foundry, the authorssought to evaluate how this semiconductor process would fareagainst a subset of the ITAR criteria: total dose and dose rate(DR) limits for upset and latchup.How the testing was performed is of note and appropriatefor discussion within the radiation effects community: weutilized commercial processor motherboards as both testersand bias boards, forming the basis for a suite of “stress” tests.These are software tests that stress the device and measureperformance.This work was supported in part by the NASA Electronic Parts andPackaging (NEPP) Program, NAVSEA Crane, the Defense Threat ReductionAgency (DTRA), and the National Reconnaissance Office (NRO).Kenneth A. LaBel and Martin A. Carts are with the NASA Goddard SpaceFlight Center, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-2869936, fax: 301-286-4699, email: [email protected] A. Gigliuto is with MEI Technologies, Inc., c/o the NASA GoddardSpace Flight Center, Code 561.4, Greenbelt, MD 20771 USA.Carl M. Szabo, Jr. is with Dell Services Federal Government, c/o theNASA Goddard Space Flight Center, Code 561.4, Greenbelt, MD 20771USA.Matthew Kay, Timothy Sinclair, Matthew Gadlage, Adam Duncan, andDave Ingalls are with NAVSEA Crane, Crane, IN 47522 USA.II. TEST TECHNIQUES AND SETUPA. Device Under TestThe device under test (DUT) we utilized is a modern stateof the-art dual-core processor from Advanced Micro Devices(AMD) [2]. The device part number is AMD A4-SeriesAD3300OJHXBOX (see Fig. 1). This is a 2.5 GHz dual-coreprocessor with integrated floating point unit and both level 1and level 2 caches packaged in a 905-pin lidded micro-PinGrid Array (µPGA) package. The device utilizes the Llanoprocessor core with on-chip peripherals, including a dualchannel double data rate generation-3 (DDR3) memorycontroller, a Peripheral Component Interconnect (PCI)Express 2.0 controller, and high-definition graphics controllerall in a 228 mm2 die. The device has an average thermaldesign power of 65 W. The production date code is DA1153PGN.AMD is a fabless semiconductor manufacturer. Thisspecific device is built on GLOBALFOUNDRIES’ 32 nmfabrication process located in Dresden, Germany. Thecomplementary metal oxide semiconductor (CMOS) processincludes hi-κ metal gates (HKMGs) on a partially-depletedsilicon-on-insulator (PD-SOI) substrate.Fig. 1. AMD A4-3300 series microprocessor.To be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.
Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)B. Facilities UtilizedFor total dose testing, a 60Co gamma ray source wasutilized, while a linear accelerator (LINAC) was used for doserate testing.C. Test Setup: Total DoseTraditional total dose testing typically utilizes acombination of a standalone bias board used for step stressirradiations and automated test equipment (ATE) running testvectors to provide coverage of a high percentage of functionalpaths and parametric measurements [3]. There are twoinvasive challenges for modern state-of-the-art processors(and similar complexity devices): Cost paradigm: the cost of ownership or access toappropriate ATE to adequately test the device ishigh and limited; and, Test vector access: these are usually proprietary tothe device manufacturer and the cost/schedulerequired to recreate them is prohibitive.Both of these challenges can be overcome if the devicemanufacturer is willing to partner for the test series, but thereneed to be other viable options if they will not.The solution for this test campaign was to utilize acommercial motherboard as both the tester and as the biasboard. We used a Biostar A55MLV motherboard compatiblewith the DUT [4]. As expected, this motherboard contains asignificant number of other electronics, such as peripheraldevices, memory chips, video processors, etc. This is aconcern during board-level irradiation with 60Co gamma rays.The basic concept was to perform a “semi” in-situirradiation where the motherboard was mounted in the testchamber with cable harnesses being fed to a user area2(monitor, keyboard, etc.) as per Fig. 2. The motherboard wasbooted and a series of partial stress tests were performed on ascheduled basis during irradiation. A more complete series ofstress tests were performed after irradiation steps where wechecked full processor performance and limited set ofparametric measurements. To exercise the DUT for pre- andpost-irradiation steps, two applications were utilized tosupport performance testing:1. HWiNFO64 [5]. This tool collects and displaysinformation about the hardware configuration. Part ofthat software function is the ability to monitor and logelectrical and environmental data from themotherboard, Central Processing Unit (CPU), GraphicsProcessing Unit (GPU), and other on-board sensors.These data are recorded for all tests.2. IntelBurn Test [6]. This software provides a usefulstress testing tool and benchmark. The program is agraphical user interface (GUI) front-end for a compiledexecutable that performs mathematical functions usingthe Linpack programming library, which is a softwarelibrary for performing numerical linear algebra ondigital computers [7]. This tool burdens the CPUworkload and enables the user to determine when and ifthere are flaws in the CPU’s ability to performoperations. Inconsistencies due to radiation arerecorded.A shielding setup was developed to reduce the total doseexposure on devices surrounding the processor. Fig. 3 showsthe physical configuration of the shield. Fig. 4 shows aradiographic film overlay on top of the bias board/DUT.Table I shows specific doses measurements for one of the testruns.Fig. 2. DUT electrical configuration inside irradiation chamber (DUT is beneath the air duct).To be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.
Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)3Fig. 3. Physical configuration of bias board shielding and DUT placement.When the motherboard began having anomalies andhangups, irradiation was stopped and the processor was movedto a unirradiated motherboard for checkout (full stress tests).An unirradiated processor was also periodically used as acheckout for the irradiated motherboard failure. Irradiationwould then resume as per above using the new motherboardwith the irradiated processor.TABLE I: MEASURED DOSE RATES FOR 4 MRAD(SI) e 0.090.120.080.240.470.300.11D. Test Setup: Dose RateDose rate tests were performed at NAVSEA Crane [8] usingthe linear accelerator (LINAC) in electron beam mode inaccordance with ASTM F744M-10 [9], [10], [11] in a methodsimilar to the total dose tests. ASTM was known until 2001 asthe American Society for Testing and Materials. Exposureswere made while executing IntelBurn Test software on thesame motherboard as the total dose tests. Performanceanomalies as well as board-level power consumption wererecorded. A full suite of stress tests were run post-exposure.Fig. 5 illustrates this test configuration.Fig. 4. Radiographic film overlay on bias boardTo be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.
Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)4increase with dose.Fig. 6. CPU internal temperature sensor measurement using HWiNFO.(a)Failures occurred on the shielded motherboard (bias board)indicating that peripheral integrated circuits were likelysensitive to total dose levels well under 50 krad(Si) and as lowas 1.1 krad(Si). These are devices of unknown manufacturersand fabrication processes. Replacement motherboards werethen swapped in. The authors note that the failure on theseother peripheral devices varied from board-to-board. The threemain motherboard failures were: DDR3 memory module failure, though they passedperformance testing in a TRIAD commercialmemory tester [12] post-irradiation. Failure levelsvaried by memory module, with 1.1 krad(Si) beinglowest failure level. Fan degradation at approximately 4 krad(Si) – thisrequired a motherboard swap. One copy of the motherboard failed at 9.7 krad(Si).The failure indicator was a biased, but unknownstate, which required a motherboard swap.IV. DOSE RATE RESULTS(b)Fig 5. (a) and (b) Test setup at LINAC.III. TEST RESULTSA. Total Dose ResultsFour samples have been irradiated to date using the semi insitu test method. The total dose rate used was between 5 and10 rad(Si)/s.No apparent device degradation was apparent on any of thesamples (i.e., they passed all stress tests after exposure).Cumulative dose levels for exposures ranged from 1 to17 Mrad(Si). For comparison, the ITAR level is 500 krad(Si).During irradiation, the stress testing logged increasingdevice temperature with increasing radiation. However,through use of an infrared (IR) thermometer, it wasdetermined that the DUT temperature had not variedsignificantly and it was likely a failure of the thermal diode orreadout circuitry used. Fig. 6 illustrates a sample of thisNo dose rate latchup was observed up to 2x1010 rad(Si)/s.The processor operated through the beam shot at the samedose rate, however the video display “blinked” at every beamshot, including below 5x108 rad(Si)/s – the ITAR level. Theauthors suspect this may be due to another integrated circuiton the motherboard, likely the graphics chip. Power-on-resetsto the processor occurred at about 2x109 rad(Si)/s. Theindividual beam shot results are show in Table 1I.To be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.
Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)TABLE II: RESULTS OF DR TEST RUNS.rad(Si)/secResponse To Radiation5.6x107"Video Blink" - video temporarily blanked out, butindependently recovered to normal in 2-3 sec. CPU andGPU stress test continued running. No visible artifactsin GPU window1.0x108"Video Blink"2.4x108"Video Blink"5.1x108"Video Blink"1.6x109"Video Blink"1.8x109"Video Blink"2.3 x109CPU turned off; power-on-reset (POR) to recover4.4x109CPU reset; auto recover8.2x109CPU turned off; POR to recover2.6x1010CPU turned off; POR to recoverV. DISCUSSIONThe methodology used for testing essentially was a “besteffort” method to replace traditional custom bias boards andexpensive ATE. The device manufacturers are able to affordboth the ATE and the manpower to develop the test vectorsdue to profit motives from commercial sales volumes.Radiation test groups, unfortunately, are not able to affordthese expenses and this is a novel compromise scheme toaccommodate the evaluation of advanced microelectronics.As noted, total dose and DR device tolerances exceed theITAR limits for this off-shore fabricated design. To the best ofthe authors’ knowledge, AMD has not intentionally radiationhardened the device for these environments, but thetechnology itself supports these characteristics.Historically, the tolerance of commercial digital processorshas shown increasing total dose tolerance as the feature sizehas shrunk. Table III illustrates this trend prior to this series oftests.It is also important to note the failures that did occurhappened on the other integrated circuits on the motherboard.In particular, both the potential for variability of commercialelectronics and low tolerance to total dose were observed.VI. SUMMARYWe have performed a series of total dose and dose rateirradiations on a 32 nm off-shore product using commercialmotherboards. Several takeaway points should be considered: Digital CMOS devices can definitely exceed theportions of the ITAR criteria that were tested herewithout any intentional radiation hardening. Multiple commercial support/peripheral integratedcircuits (i.e., surrounding the processor) failed atlevels well below ITAR criteria. These are likelybipolar or analog (video) functions. No single conclusion can be made as to whethercommercial technology is pushing the ITARenvelope inadvertently. Based on the results providedhere, this will depend on the technology and device.However, the potential for some devices to pushthese levels is there. The hardness assurance method used here, whileclearly not as thorough as traditional ATE, provides areasonable approach that is cost-effective.ACKNOWLEDGMENTThe authors would like to thank the NASA Electronic Partsand Packaging (NEPP) Program, NAVSEA Crane, theDefense Threat Reduction Agency (DTRA), and the NationalReconnaissance Office (NRO) for supporting this work.REFERENCES[1][2]TABLE III: HISTORICAL HARDNESS OF PROCESSOR tel80386-201 µmCHMOS IV1993Failure between5-7.5 krad(Si)[13]1995Failure between20-25 krad(Si)[14][3][4]Intel0.8 µm80486DX2-66 CHMOS V[5]IntelPentium III0.25 µm2000Failure 500 krad(Si)[15]AMD K70.18 µm2002Failure 100 krad(Si)[15]5[6][7][8]International Traffic In Arms Regulations, PART 121-THE UNITEDSTATES MUNITIONS LIST, Enumeration of Articles, § 121.1 General.The United States Munitions p121.htm, 1977.CPU World, AMD A4-Series A4-3300 - AD3300OJZ22HX /AD3300OJHXBOX, une 2013.ASTM International, ASTM F1892 - 12 Standard Guide for IonizingRadiation (Total Dose) Effects Testing of Semiconductor Devices,Active Standard ASTM F1892 Developed by Subcommittee: F01.11,Book of Standards Volume: 10.04,http://www.astm.org/Standards/F1892.htm, April 2013.Biostar Motherboard, A55MLV Ver. on.php?S ID 569#dl,Jun. 2013.Professional System Information and Diagnostics, HWiNFO32 /HWiNFO64 - Powerful system information tools for Windows,http://www.hwinfo.com, Mar. 2013.TECH SPOT Technology News and Analysis, IntelBurnTest urntest.html, Jul. 2012.LINPACK, a collection of Fortran subroutines that analyze and solvelinear equations and linear least-squares problems,http://www.netlib.org/linpack/, Jun. 2013.Federal Laboratory Consortium, Naval Surface Warfare Center - CraneDivision, Laboratory e/?id 1374, Jun. 2013.To be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.
Submitted for publication in the Data Workshop session at the 2013 Nuclear and Space Radiation Effects Conference (NSREC)[9][10][11][12][13][14][15]ASTM International, ASTM F744M - 10 Standard Test Method forMeasuring Dose Rate Threshold for Upset of Digital Integrated Circuits[Metric], Developed by Subcommittee: F01.11, Book of StandardsVolume: 10.04, http://www.astm.org/Standards/F744M.htm, April 2013.MIL-STD-883, Method 1020.1, "Dose rate induced latchup ilSpec/Docs/MILSTD-883/std883.pdf, Nov. 1991.MIL-STD-883, Method 1021.3, "Dose rate upset testing of digitalmicrocircuits, STD-883/std883.pdf, Feb. 2010.TRIAD Spectrum, commercial TRIAD Spectrum memory tester,http://www.triadspectrum.com/, 2012.K. Sahu, “Radiation Report on TRMM/GPEP Part No. MQ80386-20,PPM-93-062,” M93-062.pdf, June. 1993.Donald R. Johnson, “Total Dose Test Report on the Intel 80486DX2-66Microprocessor tested e/papers/td80486.htm, Sept. 1995.Jim Howard, Ken LaBel, Marty Carts, Ron Stattel, Charlie Rogers, TimIrwin, and Zoran Kahric, "Total Ionizing Dose Testing of the IntelPentium III (P3) and AMD K7 Microprocessors," 20802 P3 TID.pdf, Feb. 2002.To be published in Institute of Electrical and Electronics Engineers (IEEE) Nuclear and Space Radiation EffectsConference (NSREC) Radiation Effects Data Workshop proceedings and on nepp.nasa.gov.6
Express 2.0 controller, and high-definition graphics controller all in a 228 mm2 die. The device has an average thermal design power of 65 W. The production date code is DA 1153PGN. AMD is a fabless semiconductor manufacturer. This specific device is built on GLOBALFOUNDRIES' 32 nm fabrication process located in Dresden, Germany. The
