Prelminary2004.11.12FUJITSU SEMICONDUCTORDATA SHEET32-Bit Proprietary MicrocontrollerLSI Network Security SystemMB91401 DESCRIPTIONThe MB91401 is a network security LSI incorporating a Fujitsu’s 32-bit, FR-family RISC microcontroller with 10/100Base-T MAC Controller, encryption function and authentication function. The LSI contains an encryptionauthentication hardware accelerator that boosts the LSI’s performance for encryption and authentication communication (IKE/IPsec/SSL) to be demanded further.The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount ofpacket processing. In addition, the board has the External interface for high-speed data communication withvarious external hosts, USB ports as general-purpose interfaces, and various card interfaces. FEATURES Encryption and authentication processing by hardware accelerator functionThe LSI performs processing five times faster than by the conventional combination of encryption/authenticationhardware macros and software or about 400 times faster than by software only. In addition, CPU processing loadfactor to be involved in the encryption and the authentication processing can be decreased to 1/5 or less.Also, the LSI uses the embedded accelerator to execute that public-key encryption algorithm about 100 timesfaster than by software processing, which generally puts an extremely heavy load microcontrollers.(Continued) PACKAGE244-pin plastic FBGA(BGA-240P-M01)

MB91401Prelminary2004.11.12 For DES-ECB/DES-CBC/3DES-ECB/3DES-CBC mode* For MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 mode DH group: for 1 (MODP 768 bit) /2 (1024 bit)For the encryption/authentication macros, a software library is available by contacting the Fujitsu sales representative as required.* : Encryption function (DES/3DES)Method to encrypt, and to decrypt plaintext in 64 bits with code and decoding key to 56 bits. (3DES is repeatedthree times. The key can be set by 168 bits or less.) Packet filtering functionThe internal feature for L3/L4 packet filtering lets specific data pass or halts them based on address (IP/MACaddress) settings. Moreover, the function (multicast address filter function) to receive the data is provided incase of the multicast address registered besides my address, too. IEEE 802.3 compliant 10/100M MAC MII interface (for full-duplex/half-duplex) SMI interface for PHY device controlNote : The filtering function of layer 3/4 (mount on hardware).This feature determines whether to pass or discard packets when this layer 3 (network layer) IP addressesor layer 4 (transport layer) TCP/UDP port numbers match conditions. Outside interface with telecommunication facility (EXTERNAL INTERFACE)MB91401 is equipped it with the register for the communication and with mass sending and receiving FIFO thatachieves a large amount of data sending and receiving. Host functions include processing of data stored in a3 KByte receive buffer and a 1.5 KByte transmit buffer and stopping of data reception. when the buffers becomefull.This enables communication control even during data transmission and reception, thereby improving communication efficiency while reducing the CPU load. 8/16 bit data port Equipped with sending and receiving data port control function Transfer rate : 133 Mbps (Max) General Purpose IO (GPIO)The interruption can be generated in the I/O port in eight bits according to changing the input signal. Moreover,the I/O setting can be done in each bit. Memory InterfaceIt is possible to connect it with an external memory. USB Function ControllerIt can not operate as host USB. For USB FUNCTION Rev2.0FS Double Buffer Specification(Continued)2

Prelminary2004.11.12MB91401(Continued) CARD Interface (CompactFlash)The CompactFlash interface is a memory and I/O mode correspondence. It corresponds to the I/O of data suchas not only the memory card but also the communication cards. I2C Interface Master/slave sending and receiving For standard mode (100 Kbps Max)3

Prelminary2004.11.12MB91401 PIN ASSIGNMENTINDEX12345678910 11 12 13 14 15 16 17 18 19A172 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55B273 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 54C374 137 192 191 190 189 188 187 186 185 184 183 182 181 180 179 120 53D475 138 193 240 239 238 237 236 235 234 233 232 231 230 229 178 119 52E576 139 194228 177 118 51F677 140 195227 176 117 50G778 141 196226 175 116 49H879 142 197J980 143 198(TOP-VIEW)224 173 114 47K10 81 144 199(SUB240W)223 172 113 46L11 82 145 200222 171 112 45M12 83 146 201221 170 111 44N13 84 147 202220 169 110 43P14 85 148 203219 168 109 42R15 86 149 204218 167 108 41225 174 115 48T16 87 150 205 206 207 208 209 210 211 212 213 214 215 216 217 166 107 40U17 88 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 106 39V18 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 38W19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37: signal (204 lines): PLLVDD (1 line) 199: PLLVSS (1 line) 1974: VDDI (12 lines)195, 200, 203, 207, 211, 215, 1219, 223227, 231, 235, 239: VDDE (9 lines)83, 196, 202, 208, 214, 220, 226, 232, 238: VSS (16lins)1, 19, 37, 55, 193, 198, 201, 205, 209213, 217, 225, 229, 233, 237

Prelminary2004.11.12MB91401 PIN NUMBER TABLEPin NumberPin namePin NumberPin namePin NumberPin namePin Number1VSS61UDP121EXD11181Pin 79EXD9239VDDI60CFRDY120EXD8180EXD15240CFD65


Prelminary2004.11.12MB91401SYSTEM (9 pin)Pin namePin no. PolarityXINI8 I/OCircuitFunction/applicationINDClock input pinInput pin of clock generated in clock generator. 10 MHz to50 MHz frequency can be input.INITXI204NegativeINDReset input pinThis pin inputs a signal to initialize the LSI.When turning on the power supply, apply “0” to the pin untilthe clock signal input to the CLKIN pin becomes stable.All built-in registers and external pins are initialized, and thebuilt-in PLL is stopped when “0” is asserted to INITXI.NMIX206NegativeINDNMI input pinNon-Maskable Interrupt signalINT7INT6INT51508716 INDExternal interrupt input pinsThese pins input an external interrupt request signal.For external interrupt detection, set the ENIR, EIRR andELVR registers of the FR core.MDI2MDI1MDI08014279 INDMode pinsThese pins determine the operation mode of the LSI.Always set this bit to “001”.I/OCircuitINGCrystal oscillation input pinInput pin of crystal oscillation cell.OSCILLATOR (3 pin)Pin namePin no. PolarityFunction/application12 OSCC145NegativeINDCrystal oscillation control input pinOscillation control pin of crystal oscillation cell.“0” : Oscillation“1” : Oscillation stopOSCEB10 OUTGCrystal oscillation output pinOutput pin of crystal oscillation cell.I/OCircuitOSCEAPLL CONTROL (5 pin)Pin namePin no. PolarityFunction/applicationPLLS147 INDPLL/through mode (reset) switching input pin“0” : PLL through mode (oscillation stop)“1” : PLL oscillation modePLLSET1144 INDInput clock division ratio select input pin“0” : Input clock direct“1” : Input clock divided by 2PLLSET081 INDDivision ratio select input to PLL FB pin“0” : Two dividing frequency is input to the terminal FB.“1” : Four dividing frequency is input to the terminal FB.PLLBYPAS9 INDPLL bypass select input pin“0” : PLL used“1” : PLL unusedCLKSEL77 INDInput clock switching input pin“0” : XINI (External clock)“1” : Built-in OSC generating clock7

Prelminary2004.11.12MB91401ICE (9 pin)Pin namePin no.PolarityI/OCircuitFunction/applicationBREAKI76 INDEmulator break request pinThis pin inputs the emulator break request when an ICE isconnected.ICS2ICS1ICS074754 OUTFEmulator chip status pinsThese pins output the emulator status when an ICE isconnected.ICLK3 I/OBEmulator clock pinThis pin serves as the emulator clock pin when an ICE isconnected.ICD3ICD2ICD1ICD0140194139138 I/OBEmulator data pinsThese pins serve as the emulator data bus when an ICE isconnected.JTAG (5 pin)Pin namePin no.PolarityI/OCircuitTCK146 INETRST78 INETMS7 INETDI5 INEFunction/applicationJTAG test clock pinNote : Please input “1” when unused.JTAG test reset pinNote : Please input “0” when unused.TAP controller mode select pinNote : Please input “1” when unused.JTAG test data input pinJTAG test serial data input pin.Note : Please input “1” when unused.141 OUTFPin no.PolarityI/OCircuitVPD143 IN TEST3TEST2TEST1TEST084138211 INDTDOTEST (5 pin)Pin name8JTAG test data output pinJTAG test serial data output pinFunction/applicationMode pinInput “0” to this pin.Test pinInput “0000” to this pin.Note : Don’t set other than above description.

Prelminary2004.11.12UART (6 pin)Pin nameMB91401Pin no.PolarityI/OCircuitSIN1SIN08515 INDSerial data input pinsSerial data input pin of UART built-in FR core.SOUT1SOUT014986 OUTFSerial data output pinsSerial data output pin of UART built-in FR core.SCK1SCK014814 I/OBSerial clock I/O pinsSerial clock input/output pin of UART built-in FR core.PolarityI/OCircuit OUTBMEMORY IF (66 pin)Pin namePin applicationAddress output pins24 bits address signal pin.(Continued)9

Prelminary2004.11.12MB91401(Continued)Pin name10Pin 621013210031 I/OBData input/output pins32 bits data input/output signal pin.CSX6CSX1CSX01599829NegativeOUTBChip select output pins3-bit chip select signal pin.Output the “L” level when accessing to external memory.RDX27NegativeOUTBRead strobe output pinRead strobing signal pin.Output the “L” level when read te strobing output pinsWrite strobing signal pin.Output the “L” level when write accessing.MCLKO25 OUTFMemory clock output pinClock for peripheral resources pin.RDY157PositiveINDExternal RDY input pinWhen the external bus is not completed, the bus cycle canbe extended by inputting “0”.

Prelminary2004.11.12MB91401ETHERNET MAC CONTROLLER (17 pin)Pin namePin no. Polarity I/OCircuitFunction/applicationRXCLK48 INDClock input for reception pinMII sync signal during reception. The frequency is 2.5 MHzat 10 Mbps and 25 MHz at 100 Mbps.RXER113PositiveINDReceive error input pinIt is recognized that there is an error in the reception packetwhen “1” is input from the PHY device at receiving.RXDV172PositiveINDReceive data valid input pinIt is recognized that receive data is effective.RXCRS115PositiveINDCareer sense input pinThe state that the reception or the transmission is done isrecognized.RXD3RXD2RXD1RXD01144711245 INDReceive data input pins4-bit data input from PHY device.COL173PositiveINDCollision detection input pinWhen TXEN signal is active and “1”, the collision isrecognized. The collision is not recognized without theseconditions.TXCLK46 INDClock input for transfer pinIt becomes synchronous of MII when transmitting. Thefrequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.TXEN43PositiveOUTFTransfer enable output pinIt is shown that effective data is on the TXD bus. It is outputsynchronizing with TXCLK.TXD3TXD2TXD1TXD017117011144 OUTFTransfer data output pins4-bit data bus sent to the PHY device. It is outputsynchronizing with TXCLK.MDCLK222 OUTFSMI clock output pinSMI IF clock pinConnect to SMI clock input pin of PHY device.MDIO224 I/OBSMI data input/output pinConnect to SMI data of PHY device.11

Prelminary2004.11.12MB91401EXTERNAL IF (23 pin)Pin namePin NegativeINDExternal chip select input pinChip select input pin from external host.EXA116 INDExternal address input pinAddress input pin from external host.“0” : Register select“1” : FIFO data 575612154179120 I/OBExternal data input/output pinsThe I/O terminal of data bus bit of bit15 to bit8 with anexternal 711851 I/OBExternal data/GPIO input/output pinsThe I/O terminal of data bus bit of bit7 to bit0 with anexternal host.Note : When EXIS16 “0” input, it becomes the I/O terminalof GPIO7 to GPIO0.EXRDX117NegativeINDExternal read strobing input pinRead strove input pin from external hostEXWRX176NegativeINDExternal write strobing input pinWrite strove input pin from external hostEXIS1649 INDExternal data bus width select input pinBit width select pin of EXD“0” : 8 bit(Note : EXD15 to EXD8 are enabled.)“1” : 16 bitDREQRX174NegativeOUTFExternal reception data request output pinRecordable data to reception FIFO is shown.DREQTX175NegativeOUTFExternal transfer data request output pinIt is shown that there are data in transmission register andtransmission FIFO.

Prelminary2004.11.12USB IF (5 pin)Pin nameUDPMB91401Pin no.61Polarity I/OI/OCircuitFunction/applicationCUSB data D (differential) pinI/O signal pin on the plus side of the USB data.Use the LSI with 25 Ω to 30 Ω (27 Ω recommended)external series load resistors, 1.5 kΩ pull-up resistors andabout 100 kΩ resistors. Input “0” when the USB macro isunused.UDM183 I/OCUSB data D (differential) pinI/O signal pin on the minus side of the USB data.Use the LSI with 25 Ω to 30 Ω (27 Ω recommended)external series load resistors, 1.5 kΩ pull-up resistors andabout 100 kΩ resistors. Input “0” when the USB macro isunused.USBINS182 INDUSB insert input pinUSB socket input detection pin. Be sure to input “0” whennot using USB macro.D48 MHz input (external clock input) pinThis pin inputs an external 48-MHz clock signal.The USB macro operates based on this clock. Input theclock with high accuracy (as not only LSI but also a device)more than 2500 ppm. Input “0” when the USB macro is unused.DUSB clock select pinClock select pin using for USB macro“0” : Using internal clock“1” : Using UCLK48UCLK48UCLKSEL6124 ININ13

Prelminary2004.11.12MB91401CARD IF (41 pin)Pin namePin 8 I/OBCF data input/output pinsI/O data/status/command signal pin to CompactFlash FA0189132671881316623618713065186 OUTBCF address 10 to 0 output pinsAddress output CFA10 to CFA0 pins to CompactFlash cardsideBCF card enable output pinByte access output pin to CompactFlash card sideNote : Supported for access to CFD7 to CFD0.When “L” level is output, odd number byte access of theword is shown.BCF card enable output pinByte access output pin to CompactFlash card sideNote : Supported for access to CFD7 to CFD0.When “L” level is output at word access, even number byteaccess of the word is shown.When the byte is accessed, the even number byte and oddnumber byte access become possible because CFA0 andCFCE2X are combined and used by it.BCF Attribute/Common switching output pinAttribute/Common switching output pin to CompactFlashcard side“H” : Common Memory select“L” : Attribute Memory selectECard connection detect input pin : CFCD2XChecking connection pin of the socket and CompactFlashcard. It is shown that the CompactFlash card was connectedwhen this signal and CFCD1X are both input by ive185Negative123NegativeOUTOUTOUTIN(Continued)14

Prelminary2004.11.12(Continued)Pin nameCFCD1XCFVS1XCFRDY(CFIREQ)CFWAITXMB91401Pin nECard connection detect input pin : CFCD1XChecking connection pin of the socket and CompactFlashcard. It is shown that the CompactFlash card was connectedwhen this signal and CFCD2X are both input by “0”.ECF side GND input pinGND level detection pin from CompactFlash side.The “0” input to the pin assumes that the CompactFlashcard can operate at 3.3 V, setting the CFVCC3EX pin to the“L” level.ECF ready input pin : memory cardReady input pin from CompactFlash memory card side“1” : Ready“0” : Busy(CF interrupt : I/O card)Interrupt request pin of CompactFlash I/O card. It is shownthe interrupt request was done from the I/O card when inputto this signal by “0”.ECycle wait input pin during CF executionCycle wait input pin from CompactFlash card side“0” : It is shown that there is a wait demand at the cycleunder execution.“1” : It is shown that there is no wait demand at the cycleunder execution.CFVCC3EX234NegativeOUTBCF3.3 V power enable output pinOutputs “L” level when the CompactFlash card is operableat 3.3 V.The output signal enables 3.3-volt power supply to theCompactFlash card. The pin outputs “L” level only when theCFVS1X pin detects “0”; otherwise, the pin outputs “H”.CFRESET184PositiveOUTACF reset output pinReset output pin to CompactFlash card side.CompactFlash is reset at “H” output.CFOEX127NegativeOUTBCF read strobe output pinRead strove output pin to CompactFlash card (memorymode and Attribute memory area)CFWEX62NegativeOUTBCF register write output pinWrite clock output pin to CompactFlash card (register writeand Card Configuration Register area).The register write is executed at the rising edge from “L” to“H”.CFIORDX64NegativeOUTBCFIO read strobing output pinRead strove output pin to CompactFlash card (I/O mode)CFIOWRX129NegativeOUTBCFIO write strobing output pinWrite strove output pin to CompactFlash card (I/O mode)15

Prelminary2004.11.12MB91401I2C IF (2 pin)Pin namePin no.PolarityI/OCircuitSDA181 I/OBSerial data line input/output pinI2C bus data I/O pinSCL59 I/OBSerial clock line input/output pinI2C bus clock I/O pinPower Supply/GND (39 pin)Pin namePin no. pplicationPLLVDD199 PowersupplyV-EAPLL dedicated power supply pinThis pin is for 1.8 V power supply pin.PLLVSS197 GNDV-SAPLL dedicated GND PinVDDE83196202208214220226232238 PowersupplyV-E3.3 V power supply pinVDDI195200203207211215219223227231235239 PowersupplyV-E1.8 V power supply pinVSS1193755193198201205209213217221225229233237 GNDV-SGND Pin

Prelminary2004.11.12MB91401 I/O CIRCUIT TYPETypeCircuitRemarksDigital outputADigital output With pull/downCMOS level outputCMOS level inputValue of pull-down resistance approx. 33 kΩ (Typ)Digital inputDigital output]BDigital output CMOS level output CMOS level inputDigital inputD inputD inputD Differential inputD Full D outputCUSB I/OFull D outputLow D outputLow D outputDirectionSpeed(Continued)17

RemarksDigital inputEDigital inputCMOS level input With pull-up CMOS level input Value of pull-up resistance approx. 33 kΩ (Typ)Digital outputFCMOS level outputDigital outputOscillation outputControlG18Oscillation circuit

Prelminary2004.11.12MB91401 HANDLING DEVICESPreventing Latch-upWhen a voltage that is higher than VDDE and a voltage that is lower than VSS are impressed to the input terminaland the output terminal in CMOS IC or the voltage that exceeds ratings between VDDE to VSS is impressed, thelatch-up phenomenon might be caused. If latch-up occurs, the supply current increases rapidly, sometimesresulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximumrating during device operation.Separation of power supply patternAnalog PLL (APLL at the following) is installed in this LSI. The power supply for VCO and for digital is separatedin LSI so that the oscillation characteristic of APLL may receive the influence of power supply variation.Therefore, the power supply is recommended to be separated also on the mounting base. Separation of power supply pattern (recommended)Take measures to reduce impedance, for example, by using as wide a power pattern as possible.The recommendation example is shown as follows. For two power supplies (for digital and for VCO)It is advisable to provide a digital power-supply (a) and VCO power-supply (b) and connect them to the LSI’sequivalents, respectively.Figure For 2-power supply (for digital and for VCO)VDD (for digital)LSIPLLVDD (for VCO)Powersupply(a)Powersupply(b)APLLLogic partPLLVSSVSS For the common power supplyTo share a single power-supply for digital and VCO uses, it is advisable to separate the output into the digitaland VCO wiring patternsand connect them to the LSI.19

Prelminary2004.11.12MB91401Figure When you share the power supply for digital and for VCOVDD (for digital)LSIPLLVDD (for VCO)APLLPowersupply(a)Logic partPLLVSSVSSTreatment of the unused pinsLeaving unused input pins open results in a malfunction, so process the pull-up or pull-down.Treatment of OPEN pinsBe sure to use open pins in open state.Treatment of output pinsA large current may flow to an output pin left connected to the power-supply, another output pin, or to a highcapacitance load. Leaving the output pin that way for an extended period of time degrades the device. Usemeticulous care in using the device not to exceed the absolute maximum rating.About Mode (MDI2 to MDI0, VPD) pin and Test (TEST3 to TEST0) pinConnect these pins directly to VDDE or VSS. To prevent the device from entering test mode accidentally due tonoise, minimize the lengths of the patterns between individual mode pins and VDDE or VSS on the PC boardas possible and connect them with as low an impedance as possible.About power supply pinsIn products with multiple VDDE, VDDI or VSS pins, the pins of the same potential are internally connected inthe device to avoid abnormal operations including latch-up. However you must connect the pins to external powersupply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation strobesignals caused by the rise in the ground level, and to conform to the total output current rating.The power pins should be connected to VDDE, VDDI and VSS of this device at the lowest possible impedancefrom the current supply source.It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VDDE and VSS,and between VDDI and VSS near this device.Crystal Oscillator CircuitNoise near the OSCEA terminal may cause the MB91401 to malfunction.Design the circuit board so that OSCEA terminal, OSCEB terminal and the crystal oscillator, and the bypasscapacitor to ground are located as close to the device as possible.It is strongly recommended to design the PC board artwork with the OSCEA terminal and OSCEB terminalsurrounded by ground plane because stable operation can be expected with such a layout.20

Prelminary2004.11.12MB91401 CONNECTED SPECIFICATION OF MB91401 AND ICERecommended type and circuit configuration of the emulator interface connector mounting on the user system,attention when designing and wiring regulation are shown.When the flat cable is used, the combination of the connectors with housing should be selected.Recommended connector typeAttached cableFPC cablePart numberRemarksFH10A-30S-1SH (Maker : Hirose Electric Co., Ltd.) With latch Circuit compositionPlease put the dumping resistance 15 Ω in the series in the ICLK terminal signal because of the stability ofoperation when connecting it with ICE. Resistance must be mounted near the terminal ICLK of this LSI whenyou design the printed wiring board.Emulator interface connectorMB2198-0 and MB2197-01 sideUVCCVCCFUSE 1MCU for evaluationMB91401VCC15 Ω 3ICLKICS2 to ICS0ICLKICD3 to ICD0ICD3 to ICD0ICS2 to ICS0BREAKIBREAKIRST 210 kΩINITXIxRSTINFR(Open)Reset outputcircuitGNDVSS*1 : Use the line (inter connect) to flow the rating current or more.*2 : The change circuit might become necessary, and refer to “Precaution when designing”.*3 : Mount resistance near the terminal ICLK of MB91401.21

Prelminary2004.11.12MB91401 Precaution when designingWhen evaluation MCU on the user system is operated in the state that the emulator is not connected, shouldbe treated as follow each input terminal of evaluation MCU connected with the emulator interface on the usersystem.Therefore, note that the switch circuit etc, might become necessary in the user system when you design.The terminal processing in each emulator interface is shown as follows.Pin treatment of emulator interface (DSU-3)Evaluation MCU terminal namePin treatmentRSTTo be connected the RST terminal with the reset output circuit in theuser system.OthersTo open.Emulator interface wiring regulationsSignal line nameWiring regulationsICLKICS2 to ICS0ICD3 to ICD0BREAKI The total wiring length of each signal (From evaluation MCU pin to theemulator interface connector pin) is made within 50 mm. The difference of the total wiring length of each signal makes within 2 cmand the total wiring length of ICLK is the shortest.UVCC Wire the pattern with capacity more than the ratings current. Each power supply and GND may cause a short-circuit or reverse connection in between by a wrong connection of a probe. Insert a protection circuitsuch as a fuse into each power supply pattern to safeguard it.GND Connect directly with a power supply system pattern such as grandopran. Reference documentPlease match and refer to the following manual for the connection with ICE. DSU-FR Emulator MB2198-01 Hardware Manual FR20/30 series MB2197-01 Hardware Manual22

Prelminary2004.11.12MB91401JTAGThe JTAG function is installed in this LSI.Note that the terminal INITXI should be input in "L" when using JTAG.Notes when quartz vibrator is mountedThe crystal oscillation circuit built into this LSI operates by the following nwhen over toneoscillatesQuartzvibratorC1 Pin descriptionPin nameLC2C3FunctionOSCCOscillation control terminal of crystal oscillation cell (OSC)OSCEAInput terminal of crystal oscillation cell (OSC)OSCEBOutput terminal of crystal oscillation cell (OSC)When OSCCL is input, the OSCEA and OSCEB oscillate at the natural frequency of the crystal oscillator andpropagated into the LSI. Circuit constant on external substrateCircuit constantsDescriptionC1, C2, C3External load capacityLInductanceRrDumping resistance (addition if necessary)23

Prelminary2004.11.12MB91401 Reference ValueOscillation frequencyC1, C2C3LRrto 30 MHz5 pF to 33 pFNoneNoneNone20 MHz to 50 MHz5 pF to 15 pF10 nF approx.1 µH approx.NoneIt is necessary to add C3/L depending on a basic wave and the over tone characteristic of the oscillator of the20 MHz to 30 MHz belt.Note : These reference values are standards. The constant changes according to the characteristic of the quartzvibrator used. Therefore, we will recommend the initial evaluation that uses the evaluation sample to thedecision of the circuit constant. Please contact FUJITSU representatives about the evaluation sample. Notes when encryption/authentication accelarator is usedWhen using the encryption/authentication installed in this LSI, it is necessary to the following notes.32-bit data busThe encryption/authentication accelerator fetches data from the area storing data to be subject to encryption/authentication and encrypts or authenticates the data without CPU intervention. In the encryption processing,write is done in the area where it wants to store the data after the encryption is processed.MB9140132bitData Busencryption/authenticationacceleratorRAMAt the storage destination ofencryption/authenticationprocessing dataHolding request withdrawal demand function OFFWhen accessing to the storage destination of encryption/authentication processing data, the encryption/authentication accelerator should hold an internal bus of this LSI.Therefore, when the enc

The LSI contains an encryption authentication hardware accelerator that boosts the LSI’s performance for encryption and authentication commu-nication (IKE/IPsec/SSL) to be demanded further. The MAC controller has a packet filtering function that reduces the load