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USB 3.0 Connectivity using theCypress EZ-USB FX3 ControllerPLC2 FPGA DaysJune 20, 2012StuttgartMartin HeimlicherEnclustra GmbHFPGA Solution Center

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH-2-20.06.2012

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH-3-20.06.2012

Enclustra Company ProfileFPGA Design Center Quick Facts Founded in 2004 Located in the Technopark of Zurich 8 FPGA Engineers, 1 Technician, 1 Secretary Vendor-Independent FPGA Design Center Provider of FPGA Design Services HDL Firmware (VHDL, Verilog, C ) Hardware (High-Speed, Analog, RF) Embedded Software (for FPGA processors)Enclustra GmbH-4-20.06.2012

Enclustra FPGA Solution CenterHardware Solutions Mars Family SO-DIMM 67.6 x 30 mm 108 User I/Os (Digital, LVDS, MGT, Analog) 1-2 Ethernet Ports, 0-1 USB Port 3.3V Single Supply Voltage Mercury Family 56 x 54 mm 146-168 User I/Os (Digital, LVDS) 1 Ethernet Port, 1 USB Port 5-15V Single Supply Voltage Base Boards & FMC Cards Custom „Dream“ ModulesEnclustra GmbH-5-20.06.2012

Enclustra FPGA Solution CenterIP Solutions IP Cores Universal Drive Controller (DC/BLDC/SM) 2D-Accelerated Display Controller (LVCMOS/LVDS/DVI/HDMI) Camera Input Controllers (Camera Link/MIPI/LVDS) UDP Streaming Ethernet Controller (10/100/1G/10G) Resource-saving Memory Controllers (DDRx/QDRx/Flash) Available with AMBA AXI4 and Avalon-compliant interfaces IP Solutions FPGA Manager USB 3.0 Solution (Cypress EZ-USB FX3) Easy Licensing: Evaluation, Academic, Project, Site, Source Maintenance & Support Custom „Dream“ IPEnclustra GmbH-6-20.06.2012

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH-7-20.06.2012

Overview - What is new? NameData rateSymbol rateLow Speed1.5 Mbit/s1.875 Mbit/sFull Speed12 Mbit/s15 Mbit/sHi-Speed480 Mbit/s600 Mbit/sSuperSpeed4 Gbit/s (500 MB/s)5 Gbit/sUSB 3.0 is using high-speed serial signalingsimilar to PCIe and relies on proper cablingand PCB design!Enclustra GmbH-8-20.06.2012

Overview - What is new? (2)[1] With USB 3.0 two additionaldifferential pairs are introducedthat support unidirectional datatransfer at 5 Gbit/s New cables are thereforeneeded for USB 3.0 USB 2.0 cables and most plugsare compatible but force USB3.0 devices and hosts to work inUSB 2.0 mode[1]Enclustra GmbH-9-20.06.2012

Overview - Why USB 3.0?[2]Enclustra GmbH- 10 -20.06.2012

Overview - Why USB 3.0?[2]Enclustra GmbH- 11 -20.06.2012

Overview – Why USB 3.0?[2]Enclustra GmbH- 12 -20.06.2012

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH- 13 -20.06.2012

Hardware – Overview[3] General Programmable Interface II (GPIF II) allows maximum flexibility for connectingdata sources / sinks Automatic data transfer between USB and GPIF II port thanks to DMA engine ARM9 core can pre-process the data before sending to the host UART, SPI, I2C and I2S interfaces are used to load the FX3 firmware and/or configureexternal peripherals USB Charger and accessory detection (EZ-Dtect)Enclustra GmbH- 14 -20.06.2012

Hardware - CPU 32-bit, 200 MHz ARM926EJ-S core The core has direct access to 16 kB of Instruction Tightly CoupledMemory (TCM) and 8 kB of Data TCM JTAG interface for firmware download and debugging 512 kB of embedded SRAM for code and data 8 kB of instruction and data cache DMA connectivity between the various peripherals (i.e. USB, GPIF II,I2S, SPI, UART) Industry-standard development tools for ARM926EJ-S can be usedEnclustra GmbH- 15 -20.06.2012

Hardware - Application NotesAN76405 - EZ-USB FX3 Boot OptionsAN70193 - EZ-USB FX3 SPI Boot OptionAN68914 - EZ-USB FX3 I2C Boot OptionAN70707 - EZ-USB FX3 Hardware Design Guidelines and Schematic ChecklistAN77960 - Introduction to EZ-USB FX3’s High-Speed USB Host ControllerAN76348 - Migrating from EZ-USB FX2LP Based Design to EZ-USB FX3 Based DesignAN75432 - USB 3.0 EZ-USB FX3 OrientationAN75705 - Getting Started with FX3AN68829 - Slave FIFO Interface for EZ-USB FX3 : 5-Bit Address ModeAN65974 - Designing with the EZ-USB FX3 Slave FIFO InterfaceAN73304 - Booting EZ-USB FX3 over Synchronous ADMux InterfacesAN73150 - Booting EZ-USB FX3 over High-Speed USBEnclustra GmbH- 16 -20.06.2012

Software Framework[4] Application framework for FX3 provided by Cypress Host USB library with simple read and write function exists ThreadX RTOS running on FX3 GPIF II interface can be configured using GPIF II Designer softwareEnclustra GmbH- 17 -20.06.2012

Software Framework – SDK ContentCypress LibrariesApplication ExamplesDevelopment ToolsOthersHostUSB LibraryBulk Loop(Host & FX3)EclipseUSB DriverFX3 APILibraryStreamer(Host & FX3)GCC ARMCompilerDocumentationControlCenter(Host only)GPIF IIDesginerGPIF IIConfigurationExamples All necessary tools except compiler for host system are part of the SDK For on-chip debugging, an ARM9 compatible JTAG probe with GDB serveris required Application can be downloaded to RAM and I2C / SPI attached memoryover USB using the Control Center applicationEnclustra GmbH- 18 -20.06.2012

Software Framework – Host USBLibrary C and C# library available Simple read and write functionsto transfer data between hostand device Cypress demo applications canbe used as a starting point forthe application development[1]Enclustra GmbH- 19 -20.06.2012

Software Framework – C Library[5] The USB device is opened by instantiating the CCyUSBDevice class Based on the endpoint mode defined in the USB descriptor theappropriate derived CCyUSBEndpoint class is usedEnclustra GmbH- 20 -20.06.2012

Software Framework – FX3 API ThreadX RTOS enables multi-threaded applications FX3 API provides a complete framework to configure and operate the FX3 No direct access to FX3 registers and RAM necessaryEnclustra GmbH- 21 -20.06.2012

Software Framework – FX3 API ThreadX RTOS supports: Threads Message Queues Semaphores Mutex Memory Allocation Events Timer Cypress application examples can beused as a starting point for thedevelopment[1]Enclustra GmbH- 22 -20.06.2012

Software Framework – FX3 API CPU and memory initialization isdone before entering the main()function GPIOs and peripherals can beconfigured in the main() functionusing the FX3 API User application is running in its ownthread DMA channels are set up in the userapplication[1]Enclustra GmbH- 23 -20.06.2012

Memory Resources512 kB RAM partitioned into: 256 kB DMA buffer 32 kB User Data 180 kB Code 8 kB RTOS heap 8 kB Stack[4] 4 kB Interrupt and exception vectors Cypress delivered application framework andRTOS results already in 145 kB code sizeEnclustra GmbH- 24 -20.06.2012

FX3 – GPIF II Designer Software[2] Functions as master or slave Provides 256 firmware programmable states Supports 8 Bit, 16 Bit and 32 Bit parallel data bus Enables interface frequencies up to 100 MHz Supports 14 configurable control pins when 32 Bit data bus is used. All control pins canbe either input/output or bidirectional. Supports 16 configurable control pins when 16 or 8 Bit data bus is used. All control pinscan be either input/output or bidirectional.Enclustra GmbH- 25 -20.06.2012

DMA – Auto Channel[4] No CPU intervention Data cannot be modified Maximum performance Optional call-back functionalityEnclustra GmbH- 26 -20.06.2012

DMA – Manual Channel CPU can modify every data packet Interrupt driven Performance severely reduced[4]Enclustra GmbH- 27 -20.06.2012

DMA – Manual IN Channel Useful if data is read andprocessed on FX3[4]Enclustra GmbH- 28 -20.06.2012

DMA – Manual OUT Channel[4] One possible application is to send debug messages over UARTEnclustra GmbH- 29 -20.06.2012

Debugging the FX3 FX3 application can be downloaded and debugged over JTAG(e.g. Segger or Signum JTAG probe) using Eclipse and GDB serverEnclustra GmbH- 30 -20.06.2012

FX3 – Boot OptionsFX3 firmware can be loaded from various sources:[3] When using USB boot mode, the firmware is downloaded by thehost driver and therefore driver and firmware versions are alwaysmatching If the FX3 needs to work without USB connection, the firmwareimage can be stored using an external memory attached to the SPIor I2C interfaceEnclustra GmbH- 31 -20.06.2012

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH- 32 -20.06.2012

Slave Fifo Interface – Threads The FX3 slave fifo interface provides four threads that are addressed usingtwo address signals Each thread can be configured as read or write thread Flags can be assigned to a fixed thread or the currently addressed thread Each thread can be linked to a DMA channel and its associated bufferEnclustra GmbH- 33 -20.06.2012

Slave Fifo Interface – Configuration[3] FlagA and FlagB can be configured asfull/empty and watermark flags Flags can be assigned to current thread or afixed thread Data bus width can be set to 8, 16 or 32 BitEnclustra GmbH- 34 -20.06.2012

Slave Fifo Interface – FPGAImplementation Two threads are addressed using the SlFifo Addr signal One thread is used as write and one as read thread Flag A is configured as read thread empty Flag B is configured as write thread almost fullEnclustra GmbH- 35 -20.06.2012

Slave Fifo Interface – Read Timings[3]Enclustra GmbH- 36 -20.06.2012

Slave Fifo Interface – Write Timings[3]Enclustra GmbH- 37 -20.06.2012

Slave Fifo Interface – Timings[3] Data and flags are valid only 2 ns before clock edge Three-cycle latency from ADDR to DATA/FLAGS need to betaken into accountEnclustra GmbH- 38 -20.06.2012

Slave Fifo Interface – Difficulties Careful layout is required to ensure signal integrity with 32 data lines and 100MHz interface frequency. Proper timing analysis needs to be done as data and flags are valid only 2 nsbefore the rising edge of the clock. Maximum data transfer is only achievable when using auto DMA modecombined with overlapped transaction on the host side. The 256 kB DMA memory can only buffer data for 750 us at 330 MB/stransfer rate, which is insufficient considering the non-real-time nature of thehost computer. If data loss is not acceptable, additional buffering withexternal memory needs to be considered. Achievable transfer rate is still very much dependent on the employed USBhost controller, driver version and operating system. This should be gettingbetter by now as hardware and drivers are getting more mature. When using 32 Bit slave fifo mode, some peripherals like SPI and UARTcannot be used anymore.Enclustra GmbH- 39 -20.06.2012

Content Enclustra Company Profile Slave Fifo Interface Configuration USB 3.0 Overview What is new? Threads Why USB 3.0? FPGA Implementation Timings EZ-USB FX3 Hardware andSoftware Hardware Difficulties Enclustra USB 3.0 Solutions Software Framework FPGA Manager FX3 Memory Resources Mars PM3 Base Board GPIF 2 Designer Software Performance Demo DMA Configurations Debugging the FX3 Boot OptionsEnclustra GmbH- 40 -20.06.2012

Enclustra – FPGA Manager FPGA manager allows simple data transfer between host computer andAXI bus. Also enables access to I2C and SPI interfaces by high-level functionsEnclustra GmbH- 41 -20.06.2012

Enclustra – Evaluation Board (1) Designed for Mars family FPGA andEP modules 300 MB/sec data transfer rate overUSB 3.0 Suitable for prototype and seriesproduction Small solution size(p-ITX, 100x72 mm) Available in commercial andindustrial temperature gradeProduct NumberSupported Mars FPGA ModulesMA-PM3-CMA-MX1, MA-MX2, MA-AX3*, MA-ZX3*, MA-CA4* 0. 70 CMA-PM3-IMA-MX1, MA-MX2, MA-AX3*, MA-ZX3*, MA-CA4* -25. 85 CEnclustra GmbHTemperature Range- 42 -20.06.2012

Enclustra – Evaluation Board (2)Enclustra GmbH- 43 -20.06.2012

Enclustra – USB Performance DemoEnclustra GmbH- 44 -20.06.2012

Enclustra – FX3 Performance DemoEnclustra GmbH- 45 -20.06.2012

Questions?Next EventsNext events:Martin HeimlicherEnclustra [email protected] 41 43 343 39 40 Sindex Bern Embedded World26. - 28. Februar 2013Messezentrum NürnbergNewsletter: [email protected] in PDF tions/Enclustra GmbH- 46 -20.06.2012

References“AN75432 - USB 3.0 EZ-USB FX3 Orientation”, Application Note, CypressSemiconductor, www.cypress.com12“USB 3.0 Sales Pitch”, Presentation, Cypress Semiconductor, www.cypress.com“CYUSB3014 - EZ-USB FX3 SuperSpeed USB Controller”, Datasheet, CypressSemiconductor, www.cypress.com3“FX3 Programmers Manual”, Manual, Cypress Semiconductor,www.cypress.com4“Cypress CyAPI Programmer’s Reference“, Reference Manual, CypressSemiconductor, www.cypress.com5Enclustra GmbH- 47 -20.06.2012

Cypress EZ-USB FX3 Controller PLC2 FPGA Days June 20, 2012 Stuttgart Martin Heimlicher Enclustra GmbH FPGA Solution Center. Enclustra GmbH - 2 - 20.06.2012 Content Enclustra Company Profile USB 3.0 Overview . host driver and therefore