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DATA MEMORY (RAM)The uCOM- 43 contains 384 bits of static RAM for datastorage. The RAM is organized as 96 words by 4 bits, and the 96words are organized into 6 rows by 16 columns.The RAM is addressed with the contents of the 7- bit datapointer. The higher 3 bits(DPH) of the data pointer specify therow address in order to select one of 6 rows. The lower 4bits(DPL) of the data pointer specify the column address in orderto select one of 16 columns .Among the 96 words, a 4- bit word at address 79 (Hex) can bespecifically used as a software controlled 4- bit flag register.Special instructions are provided that can directly set , resetand test any of the 4 flag bits . Another 6 words at addresses 7Ato 7F can be specifically used as six 4-bit general purposeworking registers. Various instructions are provided that candirectly modify the specified working registers . The flagregister and all 6 working registers may also ·be treated asnormal RAM locations. All the uCOM - 43 instructions that workwith RAM data can commonly access all 96 locations , including theflag register and the working registers . In this case, all 96RAM locations are addressed with the 7- bit data contained in thedata pointer.RAM OrganizationCOL G L'\01A;)DRESSl3456789ABCDEFRO\\" A DDRESSFlag RegisterWorking RegistersThe uCOM - 43 instructions that work with RAM data provide thefollowing functions . The arithmetic and logical operationinstructions enable binary addition and logical exclusive ORbetween the accumulator and RAM data. The load and store11

instructions enable data transfer a nd exchange between theaccu mu lator and RAM locations . Two t ypes of compare instructionsare provided. The CMB instr uction enables comparison of a nysingle bit between the accu mu lator and RA da ta . The progra skips the next instruction if t he compared two bits are e qu al.The CM instruction enables comparison of 4-bit data between th eaccumulato r and a RAM loca tio n. The program skips the nextinstruction if both 4- bit data are eq ual .There are two instructions that man ip ulate and test 4- bitRAM data. The INM instruction incre ment s 4-bit data in a RAMlocation and the progr a m s kips if the 4-bit data is wrappedaround to zero . The DEX in str uction decrements 4-bit data i n aRAM location and t he prog ra m skips if the 4- bit data isdecre mented to F (Hex) .I n order to prov1ae e ffi cient use of the memo ry space, bitset, reset and test ca abilities are provided for any single bitin any RA location . Th e SMB instr uction sets and the RMBinst r uction resets a si ngle bit in a desired RAM location . TheTMB instruction tests any s ingle bit in a desired RAM locationand the next instruction is ski ped if the test ed bit is a on e(1) RA ADADSADCEXLDATAMA � TMDDEMSMBRMBPOINT ER (DP)The 7-bit data pointe r addresses one of 96 RAM (dat a me mo ry )locations . The higher 3 bit s (9PH) of the data pointer is a3- bit register and its contents s pecify a row address to se l ectone of 6 r ows . The lower 4 bi ts (DPL) of the data oointer is a4-bit up/down counter which specifies a column address to selectone of 16 columns .12

Data Pointer and RAMDPHDPL3 Bi ts4 Bits[ I I II I IIJlLData PointerCOLli\I?\ ADDRESS0 1 2 3 4 567S9 ABCD EF' O L .LL Jl ( · -rII3IitI'I1I - - 1 - I -'-r- -t - - - : .! , .}Decrement11I (u,1 - r-t - "'"T-1- -t - 1-2 L 1---LROW ADDRESSjIncrement-- - -L -- r-- - L.-, ---- - -r- - -r -t- - -i- f - 1 - - ,- L-:- -:* ) Skip a fter increment .** ) Skip afte r decremen t.In ord er to p ro vide powerfu l and flexib1e RAM addressi ng, avariety of instruct ions are provided th at modify , incremen t ,decre ment , transfer , exchange , load i mmediate and test thecontents of t he data pointer .The lower 2 bits of DPH can be logical e xc l u sive-OR ' ed witht he 09erand ( 1M0 ) of the L , XM, XM D and XMI ins t ructions .Exa mples of DPH Modific ation.1)Row address specifie d by DPH is modified from 1 to 3.DPH 0 0 11 0(EXOR) MlM0 DPH2) (Before modifica tion)(Aft er modifica tion)0 1 lRow addre ss specifie d by DPH is modi fied f rom 7 to 4 .DPH 1 1 11 1(EXOR) MlM0 DPH l(Before modifica tion)(Aft er modific ation)0 013

The DPL is composed of a 4-bit up/down counter and can beincre mented ( l), decremented (-1) and tested with instructions.The XI, XMI and IND instructions increment the contents of DPLand the next instruction is skipped if the contents of DPL arewrapped around to zero. The XD, XMD and DED instructionsdecrement the contents of DPL and the next instruction is skippedif the contents of DPL reach F (Hex) .Examples.1)Increment DPL and skip using XI, XMI or I NDinstructions.(B efore increment)(After i ncrement)DPLDPLe e1 1 1 1 (F)0 0 0 0 (0)t)1 0 c2 0 1 1 (3)Non -s kipSkip nextinstruction.2)Decrement DFL and s kip usi ng XD, XMD or DEDinstructions .(Before decrement)(Af ter decre ment)DPLDPL0 0 1 0 ( 2)0 0 0 1 (1)1 1 1 1 (F)Non -s kip0 0 0 0(0)Skip nextinstruction.These i nstruction s i ncr e ment, decre ment a n l test-and-skipfu nctions for th e DPL will enable eff icien t p rogra mm ing ofco unting loops s uch as tho se u sed in digi t co unting forarithmetic operations. Th e contents i n the data pointer and t hewo rki ng registers ca n be exc hanged by the working registeri nstr uctions . The XHX and XHR instr uctions e xc h ange the conten tsof DPH a nd the X a nd R registers, respectively. The XLY and XLSinstr uctio ns exchange t he contents of DPL and the Y and Sregi ste rs , respectively. With t hese i nstructions , t he datapo i nter contents ca n be sa ved upon interr u pt acknowledge and t hewor k i ng registers co ntent s can be stored in the data pointe r ifne cessar y during arit hmetic operations .Direct and i ndirec t RAM addressing is also made availablewit h data poi nt er manipulation instr uctions. Th e LDI i nstr uctio nloads the data pointer with 7 bit s of i mmediate data, a nd t he LDZinstr uc t i o n loads DPH with 0 a nd DPL with 4 bit s of i mmed iatedata for direct RAM a ddres si ng . Th e TAL and TLA instructionsenable 4-bit data tra nsfer betwe en t h e DPL a nd the acc umu lator.These i nstr uctions p ro vid e indirect RAM addressing using t hecontent s of accu mul ator.14

With the compare instruction CLI , the contents in DPL and4- bits of immediate data can be compared and tested . If both areequal , the next instruction is skipped .The contents in DPL are also used to select one of 9input/output ports in input/outpu t instructions such as SPB, RPE ,TPB , OP and IP .USES OF THE DPL REGISTERCounti ng Loops (XI , XMI , IND, XD, XMD, DED)Interrupt Saving of DPL (XLY , XLS)Saving of Working Register (XLY , XLS )Dir ect RAM Addressi ng (LDI , LDZ)Indirect RAM Addressing (TAL, TLA)Immediate Comparison (CLI)1/0 Selection (SPB , RPB, TPB , OP , IP)STACK REGISTERThe stack register is a last-in-first - out (LI FO) push downstack register organi zed as 3 words by 11 bits . This register isused to sa ve the contents of the 11-bit program counter (returnaddress) when a subroutine is called or an interrupt isacknowledged. The stack register enables 3 levels of stacking ofreturn addresses. All 3 levels may be u sed for nesting o fsubroutines unless the s y st em is interrupt driven . Then a levelin t he stac k register may be used to save the return address foran interru9t service ?.nd the other 2 levels may be used fors ub routine nesting. If more than 3 level s of return addressesare ne sted, the first - in address is lost.The contents of the rogra counte r is pushed onto the stackwhen a s ubroutine is called with the CZF or CAL instruction andwhen an interrupt is acknowledged . The stacked return address isrestored to the program co unte r when the program is returned withan RT or RTS i nstruction.15

ALU AND ACCUMULATOR (ACC)The ALU (arithmetic logic unit) and the accumulator (ACC)form the heart of the uCOM - 43 microcomputer system . The ALUperforms arithmetic and log ical operations and tests foroperation results. The resu l t of an o eration by the ALU isstored in the ACC and in the carry F/F . The ACC is a 4- bitregister which stores ALU results and other data to be processed.The carry F/F is a 1- bit flip - flop which indicates when a carrybit is generated during addition.ALU and AccumulatorAAceA I aThe ALU can perform the following functions as specified byappropriate instructions.Binary addition.Comparison.Increment ( l) and decrement (-1).Bit test.Logical exclusive OR.Complement.Decimal adjustment for addition ( 6)and subtraction ( 10) .16

ADThree instr uctio ns are provi ded for binar y addit ion . Theerdata pointi nstru ction adds t he me mo ry data poi n ted to by theadd thensuctioinstrADCndaADSThe.to the Ace in binar ytoget hermemo ry data point ed to by t he data point er to the Ace ted by t hewith t he carry bit in binar y . The carry F/ F is affec arith me tic(Amon g theres ults of the ADS a nd ADC i nst r uctio ns .a nd ADC instr uctio nsACSonlyns,a nd logic al opera tion instr uctioaf fect the carry flag . )two'sBi nar y su bt ractio n can be done by perfo rming one's orns,uctioinstrCIAorAc omple ment addit ion wit h the u se o f th e CMrmedperfobecannres pec tiv e ly . Deci mal addit ion and subtr actioion andusing th e decim al adjus t instr ucti o n s, DAA { 6) for additnuctioinstrEXLDAS ( le) for s ubtra c ti on , respe ctive ly . Themorymeandntsconteperfo r ms l og ical exc lu si ve OR betwe en t he Acedata point ed to by th e dat a po i nte r .TheThe Ace can be i ncr e mente d ( l ) and decre me nt ed (- 1 ). nextthendaAcehetofI C instr uctio n incre ments the conte ntsed aroun d to O. ThewrappisAcetheifedskippisni nst r uct iot he nextDEC instr uctio n decre me nt s th e conte nts of t he Ace andthe RARKith.)Hex(Finstr uctio n is skipp ed if the Ace reach esrig htitboneedtrotai nst r uc tio n , t he 4- bi ts in the Ace can bethrou gh t he carry bit .The load and sto re in st ru ct ions en able dat a tr a nsf er andby theex ch a nge betwe e n the Ace a nd the RA locat ion addre ssed s of4-bitwithdata point er . The LI i nst ructio n loads t he AceThe data point er tt.an ipula tion instr uctio ns TALi ediat e data .Ace and DPL .a nd TLA provi d e a 4- bit da ta tra nsfer bet ween the nsp rovid e foructioinstrAlso, the wo rki ng r egist e r manip ul ationngworkihetandAcedata trans fer and exc hange betwe en t heregi ster s Z and W.alThe bi t manip ulatio n instr uctio n TAB enabl es cond itionnuctioinstrCMBeThAcc.thenitsk ip by testin g any singl e bitheofbitesi glanyarin?o ?ca lso 9rovi oes cond ition al s kip bythebytoedpointdataRAMtheAce with t he corre s pondi ng bi t ino ma dedata 9oint er . Oth er cond ition al skip 09era ti on s are alsn , th euctioinstrC theKithpos sible with compa re instr uctio ns.edpointtionlocaprog ra m ski ps if t he 4 b its in the Ace a nd a RAMaidesprovnuctioto by the dat a point e r are equ a l . T e CI instranandcond ition al skip by comp aring t he data in the Acei mmed iate 4-bit da ta fie ld .da taThe Ace is also used as the so u rce and desti natio n forthetr ansfe r wit h the exter nal wor ld. With the use ofAce viai npu t /ou tpu t i ns tr uc tio ns , dat a can be loade d into t heproce ssori npu t ports and the d ata g e nerat ed or proce ssed in theca n be sent out from the Ace via outpu t ports .theA 1- bit carry save F/ F (C ' ) is provi ded in a dditi on to. Thecarry F/ F (C) whic h is used in norma l progr am opera tionsthe carryofsstatutlatesthevecarry save F/F (C ' ) is used to sa17

F/F(C) upon a subroutine call or an interrupt acknowledge. TheXC instruction exchanges the contents of C and C'. The TCinstruction provides for a conditional skip on the carry F/F bytesting the carry flag and causing a skip if it is set (1).FLAG REGISTERA 4- bit word located at address 79 (Hex) in the RAM can bespecifically used as a software controlled ge neral purpose flagregister. Four types of flag ma nipulat ion instructions areprovided (SFB, RFB , FBT, FBF) . These can operate directly uponany single bit in the flag register without loading the datapointer with address 79.Flag RegisterAddress 79The SFS instruction sets and the RFB instruction resets adesired si ngl e bit in the flag register. The FBT and FBFinstructions test a single fl29 bit and ca use a skip if thetested bit is true (1) or false (C) , respectively.If more t han 4 flag bits are nece ssary, ot her RAM locationsmay be used as software controll ed flag registers. Bitma n ipulation i nstr u ctio ns are provided to set, reset and test adesired si ng le bi t in a ny RAM word addressed by the data pointer .WORKING REGISTERS (WR)The 6 words located at addresses 7A to 7F (He x ) in RAM canbe used as six 4 bit gener al purpose working registers, Z, K, S,R, Y and x, respecti vely. Kith the work i ng register anipulati o ninstructions, these working regis ters are directly addressedindependent of the data pointer.Regist rsLocation of Workingin the RAM3Row Addressfl.A C8Zy9cColumn Address180x

The working register manipulation instructions enable datatransfer and exchange between the data pointer and the workingregisters X, Y, R and S, and also between the ACC and the workingregisters Z and w. With these instructions , the workingregisters can be used to save the latest contents of the datapointer and the ACC when an interrupt is acknowledged . Theworking r egisters can al s o be used as temporary storage for theACC contents in order to ease programming in various occasions.WORKING REGISTER ABLE INTERVAL TIM ERThe uCOM - 43 contains a software prog r ammable interval timercomposed of a 6- bit polynomial counter and a 6- bit programmablebinary counter .The initial setting of the timer is done using the timer setinstruction STM, with the timer starting to count at the end ofthe STM instruction execution . The STM instruction contains 6binary bits of immediate data (IS-I0) which is loaded in the6-bit programmable binary counter upon STM instruction e xe c ution.By varying the 6- bit immediate data, one of 64 time intervals canbe prog r ammed .If the clock frequency for the uCOM - 43 is set at 400KHz, theminimum time interval is 630usec and the maximum interval is40.32msec with increments of 630usec. If a longer time intervalis necessary than available with the built- in interval timer,Interva l Timer Configura tion6- Bit Polynomi a l Counter6- Bit PrograomableBinary CounterBorrowtt tJ ISI4I2IlIOI36- Bit Immedia t e DatasSTMInstructionRQTimer F/F19

it can be obtained by using a portion of the RAM area as aThen the built-i n timer would be used as the basiccounter .timer, incrementing RAM each time it executed the basic count.The TMThe built-in interval timer has a timer F/F(TM F/F) .F/F is reset by the STM instruction and is set when the timeinte rval specifi ed by the STM instruction h as passed . To detectthe condition of the TM F/F and perform the necessary servicingwhen the time has passed, the timer test instruction TTM isThe TTM instruction tests the TM F/F and causes a skipprovided .if it is set.Thus, by use of the interval timer and the STM and TTMinstructions, program operations not related to timing can beperformed in parallel. The built-in timer eliminates the needfor an external timer circuit or a software timer, and it can beset up and detected with very simple programming steps . By theefficient use of these capabilities, the throughput of theThe interval timer canuCOM - 43 system can be greatly increased.be used to control external tasks that require ti ming control.To set up an external machine and reset it after a desiredinterval ti me , for a very si mp l e exa mpl e, the followi ng proceduremay be used.Control of External Mach ine with the TimerSet up external machine. T i rn e r s e t cs . .I -(Interval time cou.,t )(Other processing)ll .l , T i m e r rl F d e.t e c t T tReset externalTimer count startTime count end.Timer F/F set. chineUpon STMThe details of the interval ti mer are as follows:the STMtheofI0)(I5dataimmediate6-bitTheF/F are disinstructionThe interval timer is thus initialized by the STM instruction andstarts counting at the end of the STM instruction execution. The6- bit polynomial counter counts up by one at the end of everymachine cycle. One machine cycle equals 10usec if the clockEvery time the polynomial counterfrequency is set at 400KHz .20

reaches 63 in decimal , it sends a signal to t he bina ry counterand is cleared to contin ue co un ti ng to 63 again . Thus , countingf rom 1 to 63 oper a tes the basic ti me inte r val (63 x 10usec 63 0u sec at 4e0 KH z clock } .The 6- bit b i nar y counter is decreme nt ed by one whenever thes igna l is se nt fro m the polynomia l co unt er indicating itscounting up to 63. When a borrow is generated in t he binaryco un ter , co unting ce ases and the T F/ F is set. If the binaryco un ter is set to zer o (000000} with the STM i ns tr uction, it isde cremen ted by th e first si gnal fr om t he 9 olyno i al co un ter and aborrow is 9enerated . In this case, t he timer count is ended wit hthe mini mum programmable ti me int erval (630u sec} and the TM F/Fis set for detectio n by the TTM i ns tr uction . If the STMinstructio n progr a ms the binary counte r to 000031 , 63 x 10usec xIf the ma xi mum valu e 111111 is2 1 ,2 60 usec are a vail a l e.?r ogrammed, 63 x lC u sec x 64 46 ,32 eu sec are counted .The TM F/F is res et only by t he STM instructio n. Thus,unless t h e interva l ti er is reinitia li zed with the STMinstructio n , the T F/ F rernains in a set sta te . The intervaltimer can be rest ar tec even whil e t he previous ti me c ount isconti nu ed (thu s the T F/ F is in a res e t state ) by s pecify i ng anew STM i nstruction . The immediate data of new STM i nstr uct io noverrides t e ti e count in the bin ar y coun ter and t he ti mer isres ta r ted f o r the newly ?rogra rn ed ti"e interval . Thus t heprevi ou s ti mi ng i s a bo rted .Immediate Ca.ta o f S'IM I nstruction and Interval Ti.me(Whe n c 1oc k f r eque r:!EY.DecimalIIIl:mnediate Data (Binary}l. s400 KHz . }ProgramnedIntervalTi me(p.s ec )ISI4I3I2IlIO0000000l00000l1 ,26020000l01, 89062lllll039,69063ll1ll140 , 320.630.Ca lculation of programmed interval time.I Dec imalnotation of 6- b i t immedia te dat a .1) Wh en clock frequency 400KHz ;Programmed int erval time 0 . 63(I 1 )2) When clock f r equency f KHzPr ogrammed int erva l time21mse c .; 252I 1fmsec .

INPUT/OUTPUT PORTSThe uCOM - 43 has 35 input/output channels for communicationwith and control of the external world. These ports areorganized into 9 input/output ports (A to I).Eight ports (A toH) are composed of 4 bits each and the last port (I)

Single chip microcomputer for controller applications. 2,000 by 8-bit ROM for program storage. 96 by 4 - bit RAM for data storage. 35 input/output channels, . mhe re are two types of jum9 instruct io n s. The JM P instruction enables an un co nditional jump to a ny addres s in t h e ROM a