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AN 810: Intel FPGA JESD204B IPCore and ADI AD9208 HardwareCheckout ReportSubscribeSend FeedbackAN-810 2017.12.18Latest document on the web: PDF HTML

ContentsContentsIntel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report. 3Hardware Requirements.3Hardware Setup.3Hardware Checkout Methodology. 5Receiver Data Link Layer.5Receiver Transport Layer.8Descrambling. 8Deterministic Latency (Subclass 1). 9JESD204B IP Core and ADC Configurations. 11Test Results. 12Test Result Comments.20Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208Hardware Checkout Report. 21Appendix.21AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report2

AN-810 2017.12.18Intel FPGA JESD204B IP Core and ADI AD9208 HardwareCheckout ReportThe Intel FPGA JESD204B IP Core is a high-speed point-to-point serial interfaceintellectual property (IP).The JESD204B IP core has been hardware-tested with a number of selectedJESD204B-compliant ADC (analog-to-digital converter) devices.This report highlights the interoperability of the JESD204B IP core with the AD9208converter evaluation module (EVM) from Analog Devices Inc. (ADI). The followingsections describe the hardware checkout methodology and test results.Related LinksJESD204B IP Core User GuideHardware RequirementsThe hardware checkout test requires the following hardware and software tools: Intel Arria 10 GX FPGA Development Kit ADI AD9208 EVM Mini-USB cable SMA cables Clock source card capable of generating device clock frequenciesRelated LinksArria 10 GX FPGA Development KitDevelopment kit information and ordering code.Hardware SetupAn Intel Arria 10 GX FPGA Development Kit is used with the ADI AD9208 daughtercard module installed to the development board’s FMC connector. The AD9208 EVM derives power from FMC pins. The FPGA and ADC device clocks are supplied by external clock source cardthrough SMA connectors on Intel Arria 10 FPGA kit and AD9208 EVM. Both FPGA and ADC device clocks must be sourced from the same clock sourcecard with two different frequencies, one for FPGA, and one for ADC. For subclass 1, FPGA generates SYSREF for the JESD204B IP as well as theAD9208 device. SYSREF is provided to ADC through SMA connector.Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.ISO9001:2008Registered

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Figure 1.Hardware setupArria 10 GX development kitSYSREF to ADCFPGA deviceclockADC samplingclockSYNC INSYSREF inAD9208 EVMThe following system-level diagram shows how the different modules connect in thisdesign.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report4

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Figure 2.System DiagramNote:The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitterto the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IPcore in your design.Intel Arria 10 GXDevelopment KitFMC BIntel Arria 10 Device (10AX115S1F45I1SG)Top-Level RTL (jesd204b ed.sv)global rst nUser I/OPB0PatternGeneratorAvalon-STAssembler(TX TransportLayer)Avalon-ST32 bits perTransceiverLaneAvalon-STUser DataAvalon-STUser Datamgmt clkAvalon-STPatternCheckerDeassembler(RX TransportLayer)Oscillator100 MHzAvalon-ST32 bits perTransceiverLaneframe clklink clkframe clkTop-Level PlatformDesigner Systemjesd204b ed qsys.qsysJESD204BSubsystemAD9208 EVMAD9208adc sync inADCJESD204BDACInterfaceADCJESDDuplexIP CoreADCSPI SlaveSPI MasterNios IISubsystemCore PLLConversionCircuit4device clk400 MHz3Sysref generatorCLK INSMA port J6CLK OUTSMA port J7SYSREF inputADC samplingclockSMA cableSMA cableExternal Clock SourceFPGAADCdevice clock sampling clockSMA cableLane 0 - Lane 8, Lane Rate 16.0 GbpsIn this setup, where LMF 882, the data rate of transceiver lanes is 16 Gbps. Anexternal clock source card provides 400 MHz clock to the FPGA and 1600 MHzsampling clock to AD9208 device. A periodic SYSREF is generated by the FPGA andprovided to the ADC through SMA connector.Hardware Checkout MethodologyThe following section describes the test objectives, procedure, and the passingcriteria. The test covers the following areas: Receiver data link layer Receiver transport layer Descrambling Deterministic latency (Subclass 1)Receiver Data Link LayerThis test area covers the test cases for code group synchronization (CGS) and initialframe and lane synchronization (ILA).AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report5

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18On link start up, the receiver issues a synchronization request and the transmittertransmits /K/ (K28.5) characters. The Signal Tap II Logic Analyzer tool monitors thereceiver data link layer operation.Code Group Synchronization (CGS)Table 1.Test CaseCGS.1CGS Test CasesObjectiveDescriptionCheck whether syncrequest is de-assertedafter correct receptionof four successive /K/characters.The following signals in ip variant name inst phy.v aretapped: jesd204 rx pcs data[(L*32)-1:0] jesd204 rx pcs data valid[L-1:0] jesd204 rx pcs kchar data[(L*4)-1:0] (1)The following signals in ip variant name .v are tapped: rx dev sync n jesd204 rx intThe rxlink clk is used as the samplingclock for the Signal Tap.Each lane is represented by 32-bit databus in jesd204 rx pcs data signal. The32-bit data bus for is divided into 4octets.CGS.2Check full CGS at thereceiver after correctreception of anotherfour 8B/10Bcharacters.The following signals in ip variant name inst phy.v aretapped: jesd204 rx pcs errdetect[(L*4)-1:0] jesd204 rx pcs disperr[(L*4)-1:0] (1)The following signals in ip variant name .v are tapped: jesd204 rx intThe rxlink clk is used as the samplingclock for the Signal Tap.(1)L is the number of lanes.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report6Passing Criteria /K/ character or K28.5 (0xBC) isobserved at each octet of thejesd204 rx pcs data bus.The jesd204 rx pcs data validsignal is asserted to indicate datafrom the PCS is valid.The jesd204 rx pcs kchar datasignal is asserted whenevercontrol characters like /K/, /R/, /Q/, or /A/ characters areobserved.The rx dev sync n signal is deasserted after correct receptionof at least four successive /K/characters.The jesd204 rx int signal isdeasserted if there is no error.The jesd204 rx pcs errdetect,jesd204 rx pcs disperr andjesd204 rx int signals should not beasserted during CGS phase.

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Initial Frame and Lane Synchronization (ILA)Table 2.Test CaseILA.1ILA.2ILA.3(2)Initial Frame and Lane Synchronization Test CasesObjectiveDescriptionCheck whether theinitial framesynchronization statemachine entersFS DATA state uponreceiving non /K/characters.The following signals in ip variant name inst phy.v aretapped: jesd204 rx pcs data[(L*32)-1:0] jesd204 rx pcs data valid[L-1:0] jesd204 rx pcs kchar data[(L*4)-1:0] (2)The following signals in ip variant name .v are tapped: rx dev sync n jesd204 rx intThe rxlink clk is used as the samplingclock for the Signal TapEach lane is represented by 32-bit databus in jesd204 rx pcs data. The 32-bitdata bus for is divided into 4 octets. The following signals in ip variant name inst phy.v aretapped: jesd204 rx pcs data[(L*32)-1:0] jesd204 rx pcs data valid[L-1:0] (2)The following signal in ip variant name .v is tapped: jesd204 rx intThe rxlink clk is used as the samplingclock for the Signal Tap.The Nios console accesses the followingregisters: ilas octet0 ilas octet1 ilas octet2 ilas octet3The content of 14 configuration octets insecond multiframe is stored in these 32bit registers - ilas octet0, ilas octet1,ilas octet2 and ilas octet3. The following signals in ip variant name inst phy.v aretapped: jesd204 rx pcs data[(L*32)-1:0] jesd204 rx pcs data valid[L-1:0] (2)The following signals in ip variant name .v are tapped: rx somf[3:0] dev lane aligned jesd204 rx intThe rxlink clk is used as the samplingclock for the Signal Tap. Check the JESD204Bconfigurationparameters from ADCin second multiframe.Check the lanealignmentPassing Criteria /R/ character or K28.0 (0x1C) isobserved after /K/ character atthe jesd204 rx pcs data bus.The jesd204 rx pcs data validsignal must be asserted toindicate that data from the PCS isvalid.The rx dev sync n andjesd204 rx int signals aredeasserted.Each multiframe in ILAS phaseends with /A/ character or K28.3(0x7C).The jesd204 rx pcs kchar datasignal is asserted whenevercontrol characters like /K/, /R/, /Q/, or /A/ characters areobserved./R/ character is followed by /Q/character or K28.4 (0x9C) at thebeginning of second multiframe.The jesd204 rx int is deassertedif there is no error.Octets 0-13 read from theseregisters match with theJESD204B parameters in eachtest setup.The dev lane aligned is assertedupon the last /A/ character of theILAS is received, which isfollowed by the first data octet.The rx somf marks the start ofmultiframe in user data phase.The jesd204 rx int is deassertedif there is no error.L is the number of lanes.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report7

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Receiver Transport LayerTo check the data integrity of the payload data stream through the JESD204B receiverIP Core and transport layer, the ADC is configured to output PRBS-9 and Ramp testdata pattern. The ADC is also set to operate with the same configuration as set in theJESD204B IP Core. The PRBS checker/Ramp checker in the FPGA fabric checks dataintegrity for one minute.This figure shows the conceptual test setup for data integrity checking.Figure 3.Data Integrity Check Using PRBS/Ramp CheckerADCPRBS/RampGeneratorTXTransport LayerTXPHY and Link LayerRXTransport LayerJESD204B RX IP CoreFunctionPHY and Link LayerFPGAPRBS/RampCheckerTable 3.Transport Layer Test CasesTest CaseTL.1TL.2ObjectiveDescriptionCheck the transportlayer mapping usingRamp test pattern.The following signals inaltera jesd204 transport rx top.sv aretapped: jesd204 rx data validThe following signals in jesd204b ed.svare tapped: data error jesd204 rx intThe rxframe clk is used as the samplingclock for the Signal Tap.The data error signal indicates a pass orfail for the PRBS checker.Check the transportlayer mapping usingPRBS-9 test pattern.The following signals inaltera jesd204 transport rx top.sv aretapped: jesd204 rx data validThe following signals in jesd204b ed.svare tapped: data error jesd204 rx intThe rxframe clk is used as the samplingclock for the Signal Tap.The data error signal indicates a pass orfail for the PRBS checker.Passing Criteria The jesd204 rx data valid signalis asserted.The data error andjesd204 rx int signals aredeasserted.The jesd204 rx data valid signalis asserted.The data error andjesd204 rx int signals aredeasserted.DescramblingThe PRBS/Ramp checker at the receiver transport layer checks the data integrity ofdescrambler.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report8

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18The Signal Tap Logic Analyzer tool monitors the operation of the receiver transportlayer.Table 4.Descrambler Test CasesTest CaseSCR.1SCR.2ObjectiveDescriptionPassing CriteriaCheck thefunctionality of thedescrambler usingRamp test pattern.Enable scrambler at the ADC anddescrambler at the JESD204B receiverIP Core.The signals that are tapped in this testcase are similar to test case TL.1Check thefunctionality of thedescrambler usingPRBS-9 test pattern.Enable scrambler at the ADC anddescrambler at the JESD204B receiverIP Core.The signals that are tapped in this testcase are similar to test case TL.2 The jesd204 rx data valid signalis asserted.The data error andjesd204 rx int signals aredeasserted. The jesd204 rx data valid signalis asserted.The data error andjesd204 rx int signals aredeasserted. Deterministic Latency (Subclass 1)The figure below shows the block diagram of deterministic latency test setup. ASYSREF generator in the FPGA provides a periodic SYSREF pulse for both the AD9208and JESD204B IP Core. The SYSREF generator is running in the link clock domain andthe period of SYSREF pulse is configured to the desired multiframe size. The SYSREFpulse restarts the LMF counter and realigns it to the LMFC boundary.Figure 4.Deterministic Latency Test Setup Block DiagramIntel Arria 10 GXDevelopment KitFMC BIntel Arria 10 Device (10AX115S1F45I1SG)Top-Level RTL (jesd204b ed.sv)global rst nUser I/OPB0PatternGeneratorAvalon-STAssembler(TX TransportLayer)Avalon-ST32 bits perTransceiverLaneAvalon-STUser DataAvalon-STUser Datamgmt clkAvalon-STPatternCheckerDeassembler(RX TransportLayer)Oscillator100 MHzAvalon-ST32 bits perTransceiverLaneframe clklink clkframe clkDeterministicLatencyMeasurementTop-Level PlatformDesigner Systemjesd204b ed qsys.qsysJESD204BSubsystemAD9208 EVMAD9208adc sync inADCJESD204BDACInterfaceADCJESDDuplexIP CoreADCSPI SlaveSPI MasterNios IISubsystemCore PLLConversionCircuit4device clk400 MHz3Sysref generatorSignal TapCLK OUTSMA port J7CLK INSMA port J6SYSREF inputADC samplingclockSMA cableSMA cableExternal Clock SourceFPGAADCdevice clock sampling clockSMA cableLane 0 - Lane 8, Lane Rate 16.0 GbpsAN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report9

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18The deterministic latency measurement block checks deterministic latency bymeasuring the number of link clock counts between the start of de-assertion of SYNC to the first user data output.Figure 5.Deterministic Latency Measurement Timing DiagramLink clkStateUSER DATAILASSYNC rx valid1sync to rxvalid cnt23n-1nWith the setup above, four test cases were defined to prove deterministic latency. TheJESD204B IP Core does continuous SYSREF detection. The SYSREF N-shot mode isenabled on the AD9208 for this deterministic latency measurement.Table 5.Deterministic Latency Test CasesTest CaseObjectiveDescriptionPassing CriteriaDL.1Check the FPGA SYSREF singledetection.Check that the FPGA detectsthe first rising edge of SYSREFpulse.Read the status ofsysref singledet (bit[2])identifier in syncn sysref ctrlregister at address 0x54.Read the status ofcsr sysref lmfc err (bit[1])identifier in the rx err0register at address 0x60.The value of sysref singledetidentifier should be zero.The value ofcsr sysref lmfc err identifiershould be zero.DL.2Check the SYSREF capture.Check that FPGA and ADCcapture SYSREF correctly andrestart the LMF counter. BothFPGA and ADC are alsorepetitively reset.Read the value of rbd count(bit[10:3]) identifier inrx status0 register at address0x80.If the SYSREF is capturedcorrectly and the LMF counterrestarts, for every reset, therbd count value should onlydrift within 1-2 link clocks dueto word alignment.DL.3Check the latency from startof SYNC deassertion to firstuser data output.Check that the latency is fixedfor every FPGA and ADC resetand power cycle.Record the number of linkclocks count from the start ofSYNC deassertion to the firstuser data output, which is theassertion ofjesd204 rx link valid signal.The deterministic latencymeasurement block in Figure4 on page 9 has a counter tomeasure the link clock count.Consistent latency from thestart of SYNC deassertion tothe assertion ofjesd204 rx link valid signal.DL.4Check the data latency duringuser data phase.Check that the data latency isfixed during user data phase.The ramp pattern should be inperfect shape with nodistortion.continued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report10

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Test CaseObjectiveDescriptionPassing CriteriaObserve the ramp patternfrom the Signal Tap LogicAnalyzer.Related LinksTest Results on page 12JESD204B IP Core and ADC ConfigurationsThe JESD204B IP Core parameters (L, M, and F) in this hardware checkout arenatively supported by the AD9208 device's quick configuration register at address0x570. The transceiver data rate, sampling clock frequency, and other JESD204Bparameters comply with the AD9208 operating conditionsThe hardware checkout testing implements the JESD204B IP Core with the followingparameter configuration.Global setting for all configuration:Table 6.LMF N’ 16 CS 0 CF 0 Subclass 1 FPGA Management Clock (MHz) 100 Character Replacement Enabled PCS Option Soft PCSParameter inkFrameRateg (MHz)DDCenabledDecimation factorData 24011440040040040016No1PRBS-9Rampcontinued.(3)The device clock is used to clock the transceiver.(4)The frame clock and link clock is derived from the device clock using an internal PLL.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report11

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 inkFrameRateg (MHz)DDCenabledDecimation factorData 40040040016Yes2PRBS-9RampTest ResultsThe following table contains the possible results and their definition.Table 7.Results DefinitionResultDefinitionPASSThe Device Under Test (DUT) was observed to exhibit conformant behavior.PASS with commentsThe DUT was observed to exhibit conformant behavior. However, an additionalexplanation of the situation is included, such as due to time limitations only aportion of the testing was performed.FAILThe DUT was observed to exhibit non-conformant behavior.WarningThe DUT was observed to exhibit behavior that is not recommended.Refer to commentsFrom the observations, a valid pass or fail could not be determined. An additionalexplanation of the situation is included.(3)The device clock is used to clock the transceiver.(4)The frame clock and link clock is derived from the device clock using an internal PLL.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report12

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3,TL.1, TL.2, SCR.1, and SCR.2 with different values of L, M, F, K, subclass, data rate,sampling clock, link clock, and SYSREF frequencies.Table 8.Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1,and SCR.2TestLMFSCRKData rate(Gbps)ADCSamplingClock (MHz)Link ontinued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report13

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMFSCRKData rate(Gbps)ADCSamplingClock (MHz)Link Scontinued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report14

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMFSCRKData rate(Gbps)ADCSamplingClock (MHz)Link tinued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report15

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMFSCRKData rate(Gbps)ADCSamplingClock (MHz)Link PASS448811616800400PASS1882032161600400PASS withcomments(5)2882132161600400PASS 0PASS1884032161600400PASS withcomments(5)2884132161600400PASS 0PASSThe following table shows the results for test cases DL.1, DL.2, DL.3 and DL.4 withdifferent values of L, M, F, K, subclass, data rate, sampling clock, link clock andSYSREF frequencies.Table 9.Results for Deterministic Latency TestTestLMF SubclassKData rate(Gbps)SamplingClock(MHz)Link 212116/32161600400PASSLatency(Link Clock Cycles)75 (K 16)115 (K 32)115 (K 16)195 (K 32)58 (K 20)67 (K 32)73 (K 16)103 (K 32)continued.(5)Refer to Test Result Comments section for details.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report16

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMF SubclassKData rate(Gbps)SamplingClock(MHz)Link 0400PASSDL.1421120/32161600400PASSLatency(Link Clock Cycles)53 (K 20)67 (K 32)67 (K 16)99 (K 32)53 (K 20)67 (K 32)67 (K 16)99 (K 32)99 (K 16)195 (K 32)195 (K 16)323 (K 32)75 (K 16)115 (K 32)115 (K 16)195 (K 32)53 (K 20)70 (K 32)continued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report17

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMF SubclassKData rate(Gbps)SamplingClock(MHz)Link 2161600400PASSLatency(Link Clock Cycles)67 (K 16)103 (K 32)55 (K 20)67 (K 32)67 (K 16)99 (K 32)195 (K 16)323 (K 32)115 (K 16)195 (K 32)195 (K 16)323 (K 32)67 (K 16)99 (K 32)103 (K 16)163 (K 32)continued.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report18

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18TestLMF SubclassKData rate(Gbps)SamplingClock(MHz)Link 00PASSDL.4884116/32161600400PASSLatency(Link Clock Cycles)55 (K 20)67 (K 32)67 (K 16)99 (K 32)195 (K 16)323 (K 32)115 (K 16)195 (K 32)195 (K 16)323 (K 32)67 (K 16)103 (K 32)103 (K 16)163 (K 32)The following figure shows the Signal Tap waveform of the clock count from thedeassertion of SYNC to the assertion of the jesd204 rx link valid signal, the firstoutput of the ramp test pattern (DL.3 test case). The clock count measures the firstuser data output latency.AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report19

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout ReportAN-810 2017.12.18Figure 6.Deterministic Latency Measurement Ramp Test Pattern DiagramRelated LinksDeterministic Late

ADI AD9208 EVM Mini-USB cable SMA cables Clock source card capable of generating device clock frequencies Related Links Arria 10 GX FPGA Development Kit Development kit information and ordering code. Hardware Setup An Intel Arria 10 GX FPGA Development