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Technical ReferenceDPOJET Opt. PCE, PCE3, PCE4PCI Express Measurements & Setup LibraryMethods of Implementation (MOI) for Verification, Debug and CharacterizationVersion 4.6077-0267-00www.tektronix.com

DPOJET PCI Express MOI

Copyright Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its suppliersand are protected by United States copyright laws and international treaty provisions.Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publicationsupercedes that in all previously published material. Specifications and price change privileges reserved.TEKTRONIX, TEK and RT-Eye are registered trademarks of Tektronix, Inc.Copyright 2016, PCI-SIG, All Rights Reserved for Figures 47, 49, 51, 52, 54, 56, 57, 59, 61, 62, 64, 66, 67, 69,71, 72, 74, 75, 76, 77, 79.Copyright 2016, PCI-SIG, All Rights Reserved for Table 7d,7e,7f,7g,7h,7iContacting TektronixTektronix, Inc.14200 SW Karl Braun Drive or P.O. Box 500Beaverton, OR 97077 USAFor product information, sales, service, and technical support: iiiIn North America, call 1-800-833-9200.Worldwide, visit www.tektronix.com to find contacts in your area.

Methods of ImplementationRevision HistoryVersionIssue Date March-2012Added PCI Express 3.0 MOI4.0March-2013Updated to support new SDLA4.1May-2013Added R11 RefClk setup details4.2July-2013Added Rev. 2.0 & 3.0 Ref Clock Setupdetails, VBoost measurement, Gen2 Cablesupport.4.3Oct-201436, 1032, 3-6,44, 56,58-61,66Updated probing configurations for Rev3.0CEM Specification System Board in the Table 16 and DPOJET Settings is modifiedfor Unit interval measurement, updated table2 and 3 according to Base spec 3.0, PCIeAC Common Mode setup files added.4.4Apr-20154,5, 33,35, 40,42Added PCI Express 4.0 Base SpecMeasurements and limits, Setup files(table16), Required Equipment, Horizontalsetup(4.3.1), Math ure of ChangeFirst released MOI for PCI ExpressMXM test points added in setup library.Updated Algorithms for new measurements.Incorporated review commentsAdded Ref Clock Measurement in MOIAdded Compliance Pattern description asAppendix div

Methods of ImplementationContents1Introduction to the DPOJET PCI Express Setup Library.12PCI Express Specifications.32.1Differential Transmitter (TX) Output Specifications . 32.2Differential Transmitter (TX) Compliance Eye Diagrams . 62.3Differential Receiver (RX) Input Specifications . 62.4Add-In Card Transmitter Path Compliance Specifications . 92.5System Board Transmitter Path Specifications . 142.6Reference Clock Specification . 192.7MXM System Board Specifications . 232.8MXM System Board Compliance Eye Diagrams . 242.9PCI ExpressModule Specifications . 252.10MXM ExpressModule Specifications . 272.11ExpressModule System Board Transmitter Path Specifications . 282.12PCI Express External Cabling Specifications. 292.13External Cabling Receiver Path Specifications . 302.14PCMCIA ExpressCardTM Specifications . 313PCI Express Library Contents .343.14Retaining Deskew . 36Preparing to Take Measurements .384.1Required Equipment . 384.2Probing Options for Transmitter Testing . 384.2.1SMA Input Connection . 384.2.2ECB pad connection . 394.2.3Dual Port Connection . 414.3SX Scope Support . 424.4Running the Test . 4254.4.1Horizontal Setup . 434.4.2Vertical Setup:. 434.4.3Math Setup: . 44Parameter Definitions and Method of Implementation .475.1UI (Unit Interval) MOI . 475.2TX Differential Pk-Pk Output Voltage MOI . 485.3TX De-Emphasis Ratio . 48

Methods of Implementation5.4TX Minimum Pulse Width MOI . 505.5TX Rise/Fall Time Mismatch MOI . 515.6Minimum TX Eye Width MOI . 515.7TX Median-to-Max Jitter MOI . 535.8VRX Max-Min Ratio (Voltage) MOI. 545.9TX SSC Frequency Deviation MOI . 555.10TX Rise Time MOI . 565.11TX Fall Time MOI . 575.12Data Dependent Jitter MOI(TTX-DDJ) . 585.13Uncorrelated Total Jitter (TTX-UTJ) . 605.14Uncorrelated Deterministic Jitter(TTX-UDJDD). 615.15Uncorrelated Total Pulse Width Jitter (TTX-UPW-TJ) . 635.16Uncorrelated Deterministic Pulse Width Jitter (TTX-UPW-DJDD) . 645.17Voltage swing with No Equalizer (VTX-NO-EQ) . 665.18P-P voltage swing in EIEOS sequence (VTX-EIEOS) . 675.19Effective Tx package Loss ratio(Ps21TX) . 685.20Maximum Boost Ratio(V-Tx-Boost) . 695.21Pk-Pk RefClk Jitter for Common RefClk architecture, Gen1 . 705.22RMS RefClk HF Jitter for Common RefClk architecture, Gen2 . 735.23RMS RefClk LF Jitter for Common RefClk architecture, Gen2. 765.24RMS RefClk HF Jitter for Data Clocked Rx RefClk architecture, Gen2 . 795.25RMS RefClk LF Jitter for Data Clocked Rx RefClk architecture, Gen2 . 825.26RMS RefClk Jitter for Common RefClk architecture, Gen3. 855.27RMS RefClk Worst Case Jitter for Common RefClk architecture, Gen3 . 875.28RMS RefClk Jitter for Data Clocked Rx architecture, Gen3 . 895.29RMS RefClk Worst Case Jitter for Data Clocked Rx architecture, Gen3 . 915.30RMS RefClk Jitter for Separate RefClk with Independent SSC Gen3/4. 925.31RMS RefClk Jitter for Separate RefClk with no SSC Gen3/4 . 945.32RMS RefClk Jitter for Separate RefClk with Independent SSC Gen2 . 955.33RMS RefClk Jitter for Separate RefClk with no SSC Gen2 . 986Appendix A .987Appendix B .1168Appendix C .1228.1Updated Limit Files . 122vi

Methods of Implementation8.1New Limit Files and Limits . 1239Appendix D: Compliance Pattern .12510Appendix D: AC Common Mode Filter Design .126Figure Table:Figure 1: PCI Express Transmitter Eye Mask Definitions. 6Figure 2: Receiver input eye mask . 8Figure 3: Add-in card compliance eye masks . 11Figure 4: Setup File Selection . 11Figure 5: Serial Data Link Analysis window . 12Figure 6: Setup file selection in SDLA. 12Figure 7: DPOJET Measurement Results . 13Figure 8: System Board Compliance Eye Masks. 16Figure 9: Setup File Selection . 16Figure 10: Serial Data Link Analysis window . 17Figure 11: Setup file selection in SDLA. 17Figure 12: DPOJET Measurement Results . 18Figure 13: Filter settings in Math menu . 19Figure 14: Selecting CTLE Filter. 19Figure 13: MXM System Board Compliance Eye Masks . 24Figure 14: ExpressModule add-in card compliance eye masks . 26Figure 15: MXM System Board Compliance Eye Masks . 28Figure 16: ExpressModule system board compliance eye masks. 29Figure 17: Cable (transmitter side) compliance eye masks . 30Figure 18: Cable (receiver side) compliance eye masks . 31Figure 19: ExpressCard Module Transmitter compliance eye masks. 32Figure 20: ExpressCard Host System compliance eye masks . 33Figure 21: Retaining deskew setting unchanged . 37Figure 22: Source Configuration window . 42Figure 24: Acquisition setup . 43Figure 25: Vertical Setup . 44Figure 26: Channel Deskew . 44Figure 27: Math Setup . 44Figure 28: Recall the desired file from the Setup Library. 45

Methods of ImplementationFigure 29: Setting DPOJET measurements . 45Figure 30: Displaying results in DPOJET panel. . 46Figure 31: Configure Panel . 52Figure 32: Signal at Receiver Reference Load Showing Min/Max Swing . 54Figure 33: Filter for SSC Frequency Deviation measurement . 56Figure 34. Rise Time Definition . 57Figure 35. Fall Time Definition . 58Figure 36: Relation between Data Edge PDF and Recovered Data Clock. . 59Figure 37: Derivation of TTX-UTJ and TTX-UDJDD . 60Figure 38: Derivation of TTX-UDJDD . 62Figure 39: Definition of TTX-UPW-TJ . 64Figure 40: Definition of TTX-UPW-DJDD . 65Figure 41: No Equalization PP Tx Voltage definition . 66Figure 42: EIEOS PP Tx Voltage definition. . 68Figure 43: Effective Tx package Loss Ratio definition. . 69Figure 44: Maximum Boost Ratio definition. . 70Figure 46: Measurement algorithm block diagram . 71Figure 47: Filter transfer function for Gen1 Common Clock Architecture. . 72Figure 49: Common RefClk Architecture, 5GT/s . 74Figure 50: Measurement algorithm block diagram . 74Figure 51: Filter transfer function for Common Clock Architecture. . 75Figure 52: Common Refclk bandwidth and damping for 5GT/s . 75Figure 53: Raw TIE versus Filtered TIE . 76Figure 54: Common RefClk Architecture . 77Figure 55: Measurement algorithm block diagram . 77Figure 56: Filter transfer function for Common Clock Architecture. . 78Figure 57: Common Refclk bandwidth and damping for 5GT/s . 78Figure 58: Raw TIE versus Filtered TIE . 79Figure 59: Data Clocked RefClk Architecture . 80Figure 60: Measurement algorithm block diagram . 80Figure 61: Filter transfer function for Common Clock Architecture. . 81Figure 62: Data Clocked Refclk bandwidth and damping for 5GT/s . 81Figure 63: Raw TIE versus Filtered TIE . 82Figure 64: Data Clocked RefClk Architecture . 83viii

Methods of ImplementationFigure 65: Measurement algorithm block diagram . 83Figure 66: Filter transfer function for Common Clock Architecture. . 84Figure 67: Data Clocked Refclk bandwidth and damping for 5GT/s . 84Figure 68: Raw TIE versus Filtered TIE . 84Figure 69: Common RefClk Architecture . 85Figure 70: Measurement algorithm block diagram . 86Figure 71: Filter transfer function for Common Clock Architecture. . 86Figure 72: Common Refclk Rx Architecture with ωn, ζ Limits. 86Figure 46: Measurement algorithm block diagram . 88Figure 47: Filter transfer function for Gen1 Common Clock Architecture. . 88Figure 48: Raw TIE versus Filtered TIE . 89Figure 74: Data Clocked Rx Architecture. 90Figure 75: Filter transfer function for Data Clocked Architecture. . 90Figure 76: Data Clocked Rx Architecture with ωn, ζ Limits . 91Figure 77: Separate RefClk with Independent SSC Architecture . 93Figure 78: Measurement algorithm block diagram . 94Figure 79: Filter transfer function for Separate RefClk with Independent SSC Architecture. 94Figure 77: Separate RefClk with Independent SSC Architecture . 96Figure 78: Measurement algorithm block diagram . 97Figure 79: Filter transfer function for Separate RefClk with Independent SSC Architecture. 97Figure A1: Add-in card compliance eye masks . 98Figure A2: Setup File Selection . 99Figure A3: Serial Data Link Analysis window . 100Figure A4: SDLA Equalizer Setup Menu . 100Figure A5: DPOJET Measurement Results . 100Figure A6: System Board Compliance Eye Masks . 101Figure A7: Setup File Selection . 101Figure A8: Serial Data Link Analysis window . 102Figure A9: SDLA Equalizer . 103Figure A10: DPOJET Measurement Results . 103Figure B1: Add-in card compliance eye masks . 116Figure B2: Setup File Selection . 116Figure B3: Serial Data Link Analysis window. 117Figure B4: Embadding Channel configuration . 117

Methods of ImplementationFigure B5: Equalizer settings . 118Figure B6: DPOJET Measurement Results . 118Figure B7: System Board Compliance Eye Masks . 119Figure B8: Setup File Selection . 119Figure B9: Serial Data Link Analysis window. 120Figure B10: Embedding compliance channel . 120Figure B10: Equalizer settings . 121Figure B11: DPOJET Measurement Results . 122x

Methods of Implementation1 Introduction to the DPOJET PCI Express SetupLibrary1This document provides the procedures for taking PCI Express measurements with Tektronix DPO/DSA70000Series Oscilloscopes with DPOJET (Jitter and Eye Analysis Tools) and probing solutions.DPOJET and its PCI Express Setup Library provide transmitter path measurements (amplitude, timing, andjitter), waveform mask, and limits testing described in multiple variants of the PCI Express specifications.Table 1 – Supported Specifications in the DPOJET Setup LibraryPCI Express Specification TitleTest Points DefinedBase SpecificationTransmitter & Receiver(Section 4.3)CEM SpecificationSystem and Add-In Card(Section 4.7)Reference Clock (Section 2.1)MXM SpecificationSystem and Module(0 & 3.5dB DeEmphasis)(Section 2.4& 2.5)Ref Clock SpecificationReference Clock(Section 2.6)Express Module SpecificationTransmitter Path and System Board (Section 5.4)PCMCIA Express Card StandardHost System TransmitterExpress Card Transmitter(Section 4.2.1.2)1External Cabling SpecificationTransmitter and Receiver Path (Section 2.12 & 2.13)External Cabling SpecificationTransmitter and Receiver Path (Section 2.12 & 2.13)Disclaimer: The tests provided in DPOJET (which are described in this document) do not guarantee PCI Express compliance. The test resultsshould be considered “Pre-Compliance”. Official PCI Express compliance and PCI-SIG Integrator List qualification is governed by the PCI-SIG(Special Interest Group) and can be achieved only through official PCI-SIG sanctioned testing.1

Methods of ImplementationPCI Express Specif

1 Introduction to the DPOJET PCI Express Setup Library1 This document provides the procedures for taking PCI Express measurements with Tektronix DPO/DSA70000 Series Oscilloscopes with DPOJET (Jitter and Eye Analysis Tools) and probing solutions. DPOJET and its PCI Express Setup Library prov